1 | # $Id$ |
---|
2 | |
---|
3 | PortSystem 1.0 |
---|
4 | name iverilog |
---|
5 | version 0.8.2 |
---|
6 | revision 1 |
---|
7 | categories science |
---|
8 | maintainers toby@opendarwin.org |
---|
9 | description Icarus Verilog |
---|
10 | long_description \ |
---|
11 | Icarus Verilog is a Verilog simulation and synthesis tool. It \ |
---|
12 | operates as a compiler, compiling source code writen in Verilog \ |
---|
13 | (IEEE-1364) into some target format. For batch simulation, the \ |
---|
14 | compiler can generate C++ code that is compiled and linked with \ |
---|
15 | a run time library (called \"vvm\") then executed as a command to \ |
---|
16 | run the simulation. For synthesis, the compiler generates netlists \ |
---|
17 | in the desired format. |
---|
18 | homepage http://www.icarus.com/eda/verilog/ |
---|
19 | platforms darwin |
---|
20 | |
---|
21 | master_sites ftp://ftp.icarus.com/pub/eda/verilog/v0.8/ |
---|
22 | distname verilog-${version} |
---|
23 | checksums md5 41650504e4460508a0800008a2628e07 |
---|
24 | |
---|
25 | configure.args mandir=\\\${prefix}/share/man |
---|
26 | destroot.destdir prefix=${destroot}${prefix} |
---|
27 | |
---|
28 | test.run yes |
---|
29 | test.target check |
---|