Ticket #28170: patch-binutils-2.20.1.diff
File patch-binutils-2.20.1.diff, 248.7 KB (added by stevecheckoway (Stephen Checkoway), 14 years ago) |
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bfd/archures.c
diff --git binutils-2.20.1.orig/bfd/archures.c binutils-2.20.1/bfd/archures.c index df73b3f..fd76c6c 100644
old new DESCRIPTION 398 398 .#define bfd_mach_msp14 14 399 399 .#define bfd_mach_msp15 15 400 400 .#define bfd_mach_msp16 16 401 .#define bfd_mach_msp20 20 401 402 .#define bfd_mach_msp21 21 403 .#define bfd_mach_msp22 22 404 .#define bfd_mach_msp23 23 405 .#define bfd_mach_msp24 24 406 .#define bfd_mach_msp241 241 407 .#define bfd_mach_msp26 26 402 408 .#define bfd_mach_msp31 31 403 409 .#define bfd_mach_msp32 32 404 410 .#define bfd_mach_msp33 33 … … DESCRIPTION 406 412 .#define bfd_mach_msp42 42 407 413 .#define bfd_mach_msp43 43 408 414 .#define bfd_mach_msp44 44 415 .#define bfd_mach_msp46 46 416 .#define bfd_mach_msp47 47 417 .#define bfd_mach_msp471 471 418 .#define bfd_mach_msp54 54 409 419 . bfd_arch_xc16x, {* Infineon's XC16X Series. *} 410 420 .#define bfd_mach_xc16x 1 411 421 .#define bfd_mach_xc16xl 2 -
binutils-2.20.1
diff --git binutils-2.20.1.orig/bfd/bfd-in2.h binutils-2.20.1/bfd/bfd-in2.h index d98c6ec..21e2645 100644
old new enum bfd_architecture 2072 2072 #define bfd_mach_msp14 14 2073 2073 #define bfd_mach_msp15 15 2074 2074 #define bfd_mach_msp16 16 2075 #define bfd_mach_msp20 20 2075 2076 #define bfd_mach_msp21 21 2077 #define bfd_mach_msp22 22 2078 #define bfd_mach_msp23 23 2079 #define bfd_mach_msp24 24 2080 #define bfd_mach_msp241 241 2081 #define bfd_mach_msp26 26 2076 2082 #define bfd_mach_msp31 31 2077 2083 #define bfd_mach_msp32 32 2078 2084 #define bfd_mach_msp33 33 … … enum bfd_architecture 2080 2086 #define bfd_mach_msp42 42 2081 2087 #define bfd_mach_msp43 43 2082 2088 #define bfd_mach_msp44 44 2089 #define bfd_mach_msp46 46 2090 #define bfd_mach_msp47 47 2091 #define bfd_mach_msp471 471 2092 #define bfd_mach_msp54 54 2083 2093 bfd_arch_xc16x, /* Infineon's XC16X Series. */ 2084 2094 #define bfd_mach_xc16x 1 2085 2095 #define bfd_mach_xc16xl 2 … … This is the 5 bits of a value. */ 4416 4426 BFD_RELOC_MSP430_16_BYTE, 4417 4427 BFD_RELOC_MSP430_2X_PCREL, 4418 4428 BFD_RELOC_MSP430_RL_PCREL, 4429 BFD_RELOC_MSP430X_SRC_BYTE, 4430 BFD_RELOC_MSP430X_SRC, 4431 BFD_RELOC_MSP430X_DST_BYTE, 4432 BFD_RELOC_MSP430X_DST, 4433 BFD_RELOC_MSP430X_DST_2ND_BYTE, 4434 BFD_RELOC_MSP430X_DST_2ND, 4435 BFD_RELOC_MSP430X_PCREL_SRC_BYTE, 4436 BFD_RELOC_MSP430X_PCREL_SRC, 4437 BFD_RELOC_MSP430X_PCREL_DST_BYTE, 4438 BFD_RELOC_MSP430X_PCREL_DST, 4439 BFD_RELOC_MSP430X_PCREL_DST_2ND, 4440 BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE, 4441 BFD_RELOC_MSP430X_S_BYTE, 4442 BFD_RELOC_MSP430X_S, 4443 BFD_RELOC_MSP430X_D_BYTE, 4444 BFD_RELOC_MSP430X_D, 4445 BFD_RELOC_MSP430X_PCREL_D, 4446 BFD_RELOC_MSP430X_INDXD, 4447 BFD_RELOC_MSP430X_PCREL_INDXD, 4419 4448 4420 4449 /* IQ2000 Relocations. */ 4421 4450 BFD_RELOC_IQ2000_OFFSET_16, -
bfd/cpu-msp430.c
diff --git binutils-2.20.1.orig/bfd/cpu-msp430.c binutils-2.20.1/bfd/cpu-msp430.c index 63c301a..8cc47cb 100644
old new static const bfd_arch_info_type arch_info_struct[] = 65 65 /* msp430x16x. */ 66 66 N (16, bfd_mach_msp16, "msp:16", FALSE, & arch_info_struct[7]), 67 67 68 /* msp430x20x. */ 69 N (16, bfd_mach_msp20, "msp:20", FALSE, & arch_info_struct[8]), 70 68 71 /* msp430x21x. */ 69 N (16, bfd_mach_msp21, "msp:21", FALSE, & arch_info_struct[8]), 72 N (16, bfd_mach_msp21, "msp:21", FALSE, & arch_info_struct[9]), 73 74 /* msp430x22x. */ 75 N (16, bfd_mach_msp22, "msp:22", FALSE, & arch_info_struct[10]), 76 77 /* msp430x23x0. */ 78 N (16, bfd_mach_msp23, "msp:23", FALSE, & arch_info_struct[11]), 79 80 /* msp430x24x including msp430x2410 */ 81 N (16, bfd_mach_msp24, "msp:24", FALSE, & arch_info_struct[12]), 82 83 /* msp430x241x except msp430x2410 (extended address range) */ 84 N (20, bfd_mach_msp241, "msp:241", FALSE, & arch_info_struct[13]), 85 86 /* msp430x26x. */ 87 N (20, bfd_mach_msp26, "msp:26", FALSE, & arch_info_struct[14]), 70 88 71 89 /* msp430x31x. */ 72 N (16, bfd_mach_msp31, "msp:31", FALSE, & arch_info_struct[ 9]),90 N (16, bfd_mach_msp31, "msp:31", FALSE, & arch_info_struct[15]), 73 91 74 92 /* msp430x32x. */ 75 N (16, bfd_mach_msp32, "msp:32", FALSE, & arch_info_struct[1 0]),93 N (16, bfd_mach_msp32, "msp:32", FALSE, & arch_info_struct[16]), 76 94 77 95 /* msp430x33x. */ 78 N (16, bfd_mach_msp33, "msp:33", FALSE, & arch_info_struct[1 1]),96 N (16, bfd_mach_msp33, "msp:33", FALSE, & arch_info_struct[17]), 79 97 80 98 /* msp430x41x. */ 81 N (16, bfd_mach_msp41, "msp:41", FALSE, & arch_info_struct[1 2]),99 N (16, bfd_mach_msp41, "msp:41", FALSE, & arch_info_struct[18]), 82 100 83 101 /* msp430x42x. */ 84 N (16, bfd_mach_msp42, "msp:42", FALSE, & arch_info_struct[1 3]),102 N (16, bfd_mach_msp42, "msp:42", FALSE, & arch_info_struct[19]), 85 103 86 104 /* msp430x43x. */ 87 N (16, bfd_mach_msp43, "msp:43", FALSE, & arch_info_struct[ 14]),105 N (16, bfd_mach_msp43, "msp:43", FALSE, & arch_info_struct[20]), 88 106 89 107 /* msp430x44x. */ 90 N (16, bfd_mach_msp43, "msp:44", FALSE, NULL) 108 N (16, bfd_mach_msp44, "msp:44", FALSE, & arch_info_struct[21]), 109 110 /* msp430x46xx. */ 111 N (20, bfd_mach_msp46, "msp:46", FALSE, & arch_info_struct[22]), 112 113 /* msp430x47x3, 47x4. */ 114 N (16, bfd_mach_msp47, "msp:47", FALSE, & arch_info_struct[23]), 115 116 /* msp430x471x6, 471x7. */ 117 N (20, bfd_mach_msp471, "msp:471", FALSE, & arch_info_struct[24]), 118 119 /* msp430x54xx, msp430x55xx. */ 120 N (20, bfd_mach_msp54, "msp:54", FALSE, NULL) 121 91 122 }; 92 123 93 124 const bfd_arch_info_type bfd_msp430_arch = -
bfd/doc/archures.texi
diff --git binutils-2.20.1.orig/bfd/doc/archures.texi binutils-2.20.1/bfd/doc/archures.texi index 33d7c59..f1f0a12 100644
old new enum bfd_architecture 363 363 #define bfd_mach_msp14 14 364 364 #define bfd_mach_msp15 15 365 365 #define bfd_mach_msp16 16 366 #define bfd_mach_msp20 20 366 367 #define bfd_mach_msp21 21 368 #define bfd_mach_msp22 22 369 #define bfd_mach_msp24 24 370 #define bfd_mach_msp241 241 371 #define bfd_mach_msp26 26 367 372 #define bfd_mach_msp31 31 368 373 #define bfd_mach_msp32 32 369 374 #define bfd_mach_msp33 33 … … enum bfd_architecture 371 376 #define bfd_mach_msp42 42 372 377 #define bfd_mach_msp43 43 373 378 #define bfd_mach_msp44 44 379 #define bfd_mach_msp46 46 374 380 bfd_arch_xc16x, /* Infineon's XC16X Series. */ 375 381 #define bfd_mach_xc16x 1 376 382 #define bfd_mach_xc16xl 2 … … See bfd_octets_per_byte. 623 629 624 630 This routine is provided for those cases where a bfd * is not 625 631 available 626 -
bfd/elf32-msp430.c
diff --git binutils-2.20.1.orig/bfd/elf32-msp430.c binutils-2.20.1/bfd/elf32-msp430.c index 7a57024..3362365 100644
old new static reloc_howto_type elf_msp430_howto_table[] = 90 90 0xffff, /* dst_mask */ 91 91 FALSE), /* pcrel_offset */ 92 92 93 /* A 16 bit absolute relocation for command address. */93 /* A 16 bit PC relative relocation for command address. */ 94 94 HOWTO (R_MSP430_16_PCREL, /* type */ 95 95 1, /* rightshift */ 96 96 1, /* size (0 = byte, 1 = short, 2 = long) */ … … static reloc_howto_type elf_msp430_howto_table[] = 120 120 0xffff, /* dst_mask */ 121 121 FALSE), /* pcrel_offset */ 122 122 123 /* A 16 bit absolute relocation for command address. */123 /* A 16 bit PC relative relocation, byte operations. */ 124 124 HOWTO (R_MSP430_16_PCREL_BYTE,/* type */ 125 125 1, /* rightshift */ 126 126 1, /* size (0 = byte, 1 = short, 2 = long) */ … … static reloc_howto_type elf_msp430_howto_table[] = 163 163 FALSE, /* partial_inplace */ 164 164 0, /* src_mask */ 165 165 0xffff, /* dst_mask */ 166 TRUE) /* pcrel_offset */ 166 TRUE), /* pcrel_offset */ 167 168 /* A 20 bit msp430x absolute src operand relocation, byte operations */ 169 HOWTO (R_MSP430X_SRC_BYTE, /* type */ 170 0, /* rightshift */ 171 2, /* size (0 = byte, 1 = short, 2 = long) */ 172 20, /* bitsize */ 173 FALSE, /* pc_relative */ 174 0, /* bitpos */ 175 complain_overflow_dont,/* complain_on_overflow */ 176 bfd_elf_generic_reloc, /* special_function */ 177 "R_MSP430X_SRC_BYTE", /* name */ 178 FALSE, /* partial_inplace */ 179 0xfffff, /* src_mask */ 180 0, /* dst_mask */ 181 FALSE), /* pcrel_offset */ 182 183 /* A 20 bit msp430x absolute src operand relocation */ 184 HOWTO (R_MSP430X_SRC, /* type */ 185 0, /* rightshift */ 186 2, /* size (0 = byte, 1 = short, 2 = long) */ 187 20, /* bitsize */ 188 FALSE, /* pc_relative */ 189 0, /* bitpos */ 190 complain_overflow_dont,/* complain_on_overflow */ 191 bfd_elf_generic_reloc, /* special_function */ 192 "R_MSP430X_SRC", /* name */ 193 FALSE, /* partial_inplace */ 194 0xfffff, /* src_mask */ 195 0, /* dst_mask */ 196 FALSE), /* pcrel_offset */ 197 198 /* A 20 bit msp430x absolute dst operand relocation, src is register mode, byte operations */ 199 HOWTO (R_MSP430X_DST_BYTE, /* type */ 200 0, /* rightshift */ 201 2, /* size (0 = byte, 1 = short, 2 = long) */ 202 20, /* bitsize */ 203 FALSE, /* pc_relative */ 204 0, /* bitpos */ 205 complain_overflow_dont,/* complain_on_overflow */ 206 bfd_elf_generic_reloc, /* special_function */ 207 "R_MSP430X_DST_BYTE", /* name */ 208 FALSE, /* partial_inplace */ 209 0, /* src_mask */ 210 0xfffff, /* dst_mask */ 211 FALSE), /* pcrel_offset */ 212 213 /* A 20 bit msp430x absolute dst operand relocation, src is register mode */ 214 HOWTO (R_MSP430X_DST, /* type */ 215 0, /* rightshift */ 216 2, /* size (0 = byte, 1 = short, 2 = long) */ 217 20, /* bitsize */ 218 FALSE, /* pc_relative */ 219 0, /* bitpos */ 220 complain_overflow_dont,/* complain_on_overflow */ 221 bfd_elf_generic_reloc, /* special_function */ 222 "R_MSP430X_DST", /* name */ 223 FALSE, /* partial_inplace */ 224 0, /* src_mask */ 225 0xfffff, /* dst_mask */ 226 FALSE), /* pcrel_offset */ 227 228 /* A 20 bit msp430x absolute dst operand relocation, byte operations */ 229 HOWTO (R_MSP430X_DST_2ND_BYTE, /* type */ 230 0, /* rightshift */ 231 2, /* size (0 = byte, 1 = short, 2 = long) */ 232 20, /* bitsize */ 233 FALSE, /* pc_relative */ 234 0, /* bitpos */ 235 complain_overflow_dont,/* complain_on_overflow */ 236 bfd_elf_generic_reloc, /* special_function */ 237 "R_MSP430X_DST_2ND_BYTE", /* name */ 238 FALSE, /* partial_inplace */ 239 0, /* src_mask */ 240 0xfffff, /* dst_mask */ 241 FALSE), /* pcrel_offset */ 242 243 /* A 20 bit msp430x absolute dst operand relocation */ 244 HOWTO (R_MSP430X_DST_2ND, /* type */ 245 0, /* rightshift */ 246 2, /* size (0 = byte, 1 = short, 2 = long) */ 247 20, /* bitsize */ 248 FALSE, /* pc_relative */ 249 0, /* bitpos */ 250 complain_overflow_dont,/* complain_on_overflow */ 251 bfd_elf_generic_reloc, /* special_function */ 252 "R_MSP430X_DST_2ND", /* name */ 253 FALSE, /* partial_inplace */ 254 0, /* src_mask */ 255 0xfffff, /* dst_mask */ 256 FALSE), /* pcrel_offset */ 257 258 /* A 20 bit msp430x PC relative src operand relocation, byte operations */ 259 HOWTO (R_MSP430X_PCREL_SRC_BYTE, /* type */ 260 0, /* rightshift */ 261 2, /* size (0 = byte, 1 = short, 2 = long) */ 262 20, /* bitsize */ 263 TRUE, /* pc_relative */ 264 0, /* bitpos */ 265 complain_overflow_dont,/* complain_on_overflow */ 266 bfd_elf_generic_reloc, /* special_function */ 267 "R_MSP430X_PCREL_SRC_BYTE", /* name */ 268 FALSE, /* partial_inplace */ 269 0xfffff, /* src_mask */ 270 0, /* dst_mask */ 271 TRUE), /* pcrel_offset */ 272 273 /* A 20 bit msp430x PC relative src operand relocation */ 274 HOWTO (R_MSP430X_PCREL_SRC, /* type */ 275 0, /* rightshift */ 276 2, /* size (0 = byte, 1 = short, 2 = long) */ 277 20, /* bitsize */ 278 TRUE, /* pc_relative */ 279 0, /* bitpos */ 280 complain_overflow_dont,/* complain_on_overflow */ 281 bfd_elf_generic_reloc, /* special_function */ 282 "R_MSP430X_PCREL_SRC", /* name */ 283 FALSE, /* partial_inplace */ 284 0xfffff, /* src_mask */ 285 0, /* dst_mask */ 286 TRUE), /* pcrel_offset */ 287 288 /* A 20 bit msp430x PC relative dst operand relocation, src is register mode, byte operations */ 289 HOWTO (R_MSP430X_PCREL_DST_BYTE, /* type */ 290 0, /* rightshift */ 291 2, /* size (0 = byte, 1 = short, 2 = long) */ 292 20, /* bitsize */ 293 TRUE, /* pc_relative */ 294 0, /* bitpos */ 295 complain_overflow_dont,/* complain_on_overflow */ 296 bfd_elf_generic_reloc, /* special_function */ 297 "R_MSP430X_PCREL_DST_BYTE", /* name */ 298 FALSE, /* partial_inplace */ 299 0, /* src_mask */ 300 0xfffff, /* dst_mask */ 301 TRUE), /* pcrel_offset */ 302 303 /* A 20 bit msp430x PC relative dst operand relocation, src is register mode */ 304 HOWTO (R_MSP430X_PCREL_DST, /* type */ 305 0, /* rightshift */ 306 2, /* size (0 = byte, 1 = short, 2 = long) */ 307 20, /* bitsize */ 308 TRUE, /* pc_relative */ 309 0, /* bitpos */ 310 complain_overflow_dont,/* complain_on_overflow */ 311 bfd_elf_generic_reloc, /* special_function */ 312 "R_MSP430X_PCREL_DST", /* name */ 313 FALSE, /* partial_inplace */ 314 0, /* src_mask */ 315 0xfffff, /* dst_mask */ 316 TRUE), /* pcrel_offset */ 317 318 /* A 20 bit msp430x PC relative dst operand relocation, byte operations */ 319 HOWTO (R_MSP430X_PCREL_DST_2ND_BYTE, /* type */ 320 0, /* rightshift */ 321 2, /* size (0 = byte, 1 = short, 2 = long) */ 322 20, /* bitsize */ 323 TRUE, /* pc_relative */ 324 0, /* bitpos */ 325 complain_overflow_dont,/* complain_on_overflow */ 326 bfd_elf_generic_reloc, /* special_function */ 327 "R_MSP430X_PCREL_DST_2ND_BYTE", /* name */ 328 FALSE, /* partial_inplace */ 329 0, /* src_mask */ 330 0xfffff, /* dst_mask */ 331 TRUE), /* pcrel_offset */ 332 333 /* A 20 bit msp430x PC relative dst operand relocation */ 334 HOWTO (R_MSP430X_PCREL_DST_2ND, /* type */ 335 0, /* rightshift */ 336 2, /* size (0 = byte, 1 = short, 2 = long) */ 337 20, /* bitsize */ 338 TRUE, /* pc_relative */ 339 0, /* bitpos */ 340 complain_overflow_dont,/* complain_on_overflow */ 341 bfd_elf_generic_reloc, /* special_function */ 342 "R_MSP430X_PCREL_DST_2ND", /* name */ 343 FALSE, /* partial_inplace */ 344 0, /* src_mask */ 345 0xfffff, /* dst_mask */ 346 TRUE), /* pcrel_offset */ 347 348 /* A 20 bit msp430x address instructions immediate src operand relocation */ 349 HOWTO (R_MSP430X_S_BYTE, /* type */ 350 0, /* rightshift */ 351 2, /* size (0 = byte, 1 = short, 2 = long) */ 352 20, /* bitsize */ 353 FALSE, /* pc_relative */ 354 0, /* bitpos */ 355 complain_overflow_dont,/* complain_on_overflow */ 356 bfd_elf_generic_reloc, /* special_function */ 357 "R_MSP430X_S_BYTE", /* name */ 358 FALSE, /* partial_inplace */ 359 0xfffff, /* src_mask */ 360 0, /* dst_mask */ 361 FALSE), /* pcrel_offset */ 362 363 /* A 20 bit msp430x address instructions absolute src operand relocation */ 364 HOWTO (R_MSP430X_S, /* type */ 365 0, /* rightshift */ 366 2, /* size (0 = byte, 1 = short, 2 = long) */ 367 20, /* bitsize */ 368 FALSE, /* pc_relative */ 369 0, /* bitpos */ 370 complain_overflow_dont,/* complain_on_overflow */ 371 bfd_elf_generic_reloc, /* special_function */ 372 "R_MSP430X_S", /* name */ 373 FALSE, /* partial_inplace */ 374 0xfffff, /* src_mask */ 375 0, /* dst_mask */ 376 FALSE), /* pcrel_offset */ 377 378 /* A 20 bit msp430x address instructions immediate dst operand relocation */ 379 HOWTO (R_MSP430X_D_BYTE, /* type */ 380 0, /* rightshift */ 381 2, /* size (0 = byte, 1 = short, 2 = long) */ 382 20, /* bitsize */ 383 FALSE, /* pc_relative */ 384 0, /* bitpos */ 385 complain_overflow_dont,/* complain_on_overflow */ 386 bfd_elf_generic_reloc, /* special_function */ 387 "R_MSP430X_D_BYTE", /* name */ 388 FALSE, /* partial_inplace */ 389 0, /* src_mask */ 390 0xfffff, /* dst_mask */ 391 FALSE), /* pcrel_offset */ 392 393 /* A 20 bit msp430x address instructions absolute dst operand relocation */ 394 HOWTO (R_MSP430X_D, /* type */ 395 0, /* rightshift */ 396 2, /* size (0 = byte, 1 = short, 2 = long) */ 397 20, /* bitsize */ 398 FALSE, /* pc_relative */ 399 0, /* bitpos */ 400 complain_overflow_dont,/* complain_on_overflow */ 401 bfd_elf_generic_reloc, /* special_function */ 402 "R_MSP430X_D", /* name */ 403 FALSE, /* partial_inplace */ 404 0, /* src_mask */ 405 0xfffff, /* dst_mask */ 406 FALSE), /* pcrel_offset */ 407 408 /* A 20 bit msp430x address instructions absolute dst operand relocation */ 409 HOWTO (R_MSP430X_PCREL_D, /* type */ 410 0, /* rightshift */ 411 2, /* size (0 = byte, 1 = short, 2 = long) */ 412 20, /* bitsize */ 413 TRUE, /* pc_relative */ 414 0, /* bitpos */ 415 complain_overflow_dont,/* complain_on_overflow */ 416 bfd_elf_generic_reloc, /* special_function */ 417 "R_MSP430X_PCREL_D", /* name */ 418 FALSE, /* partial_inplace */ 419 0, /* src_mask */ 420 0xfffff, /* dst_mask */ 421 TRUE), /* pcrel_offset */ 422 423 /* A 16 bit msp430x relocation *** for msp430x calla 16-bit PC-relative index ***/ 424 HOWTO (R_MSP430X_PCREL_INDXD, /* type */ 425 0, /* rightshift */ 426 1, /* size (0 = byte, 1 = short, 2 = long) */ 427 16, /* bitsize */ 428 TRUE, /* pc_relative */ 429 0, /* bitpos */ 430 complain_overflow_dont,/* complain_on_overflow */ 431 bfd_elf_generic_reloc, /* special_function */ 432 "R_MSP430X_PCREL_INDXD", /* name */ 433 FALSE, /* partial_inplace */ 434 0xffff, /* src_mask */ 435 0xffff, /* dst_mask */ 436 TRUE), /* pcrel_offset */ 437 438 /* A 16 bit msp430x relocation *** for msp430x bra/calla 16-bit index ***/ 439 HOWTO (R_MSP430X_INDXD, /* type */ 440 0, /* rightshift */ 441 1, /* size (0 = byte, 1 = short, 2 = long) */ 442 16, /* bitsize */ 443 FALSE, /* pc_relative */ 444 0, /* bitpos */ 445 complain_overflow_dont,/* complain_on_overflow */ 446 bfd_elf_generic_reloc, /* special_function */ 447 "R_MSP430X_INDXD", /* name */ 448 FALSE, /* partial_inplace */ 449 0xffff, /* src_mask */ 450 0xffff, /* dst_mask */ 451 FALSE), /* pcrel_offset */ 167 452 }; 168 453 169 454 /* Map BFD reloc types to MSP430 ELF reloc types. */ … … static const struct msp430_reloc_map msp430_reloc_map[] = 185 470 {BFD_RELOC_MSP430_16_PCREL_BYTE, R_MSP430_16_PCREL_BYTE}, 186 471 {BFD_RELOC_MSP430_16_BYTE, R_MSP430_16_BYTE}, 187 472 {BFD_RELOC_MSP430_2X_PCREL, R_MSP430_2X_PCREL}, 188 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL} 473 {BFD_RELOC_MSP430_RL_PCREL, R_MSP430_RL_PCREL}, 474 475 {BFD_RELOC_MSP430X_SRC_BYTE, R_MSP430X_SRC_BYTE}, 476 {BFD_RELOC_MSP430X_SRC, R_MSP430X_SRC}, 477 {BFD_RELOC_MSP430X_DST_BYTE, R_MSP430X_DST_BYTE}, 478 {BFD_RELOC_MSP430X_DST, R_MSP430X_DST}, 479 {BFD_RELOC_MSP430X_DST_2ND_BYTE, R_MSP430X_DST_2ND_BYTE}, 480 {BFD_RELOC_MSP430X_DST_2ND, R_MSP430X_DST_2ND}, 481 482 {BFD_RELOC_MSP430X_PCREL_SRC_BYTE, R_MSP430X_PCREL_SRC_BYTE}, 483 {BFD_RELOC_MSP430X_PCREL_SRC, R_MSP430X_PCREL_SRC}, 484 {BFD_RELOC_MSP430X_PCREL_DST_BYTE, R_MSP430X_PCREL_DST_BYTE}, 485 {BFD_RELOC_MSP430X_PCREL_DST, R_MSP430X_PCREL_DST}, 486 {BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE, R_MSP430X_PCREL_DST_2ND_BYTE}, 487 {BFD_RELOC_MSP430X_PCREL_DST_2ND, R_MSP430X_PCREL_DST_2ND}, 488 489 {BFD_RELOC_MSP430X_S_BYTE, R_MSP430X_S_BYTE}, 490 {BFD_RELOC_MSP430X_S, R_MSP430X_S}, 491 {BFD_RELOC_MSP430X_D_BYTE, R_MSP430X_D_BYTE}, 492 {BFD_RELOC_MSP430X_D, R_MSP430X_D}, 493 {BFD_RELOC_MSP430X_PCREL_D, R_MSP430X_PCREL_D}, 494 {BFD_RELOC_MSP430X_INDXD, R_MSP430X_INDXD}, 495 {BFD_RELOC_MSP430X_PCREL_INDXD, R_MSP430X_PCREL_INDXD}, 189 496 }; 190 497 191 498 static reloc_howto_type * … … bfd_elf32_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, 207 514 { 208 515 unsigned int i; 209 516 210 for (i = 0; 211 i < (sizeof (elf_msp430_howto_table) 212 / sizeof (elf_msp430_howto_table[0])); 213 i++) 517 for (i = 0; i < ARRAY_SIZE (elf_msp430_howto_table); i++) 214 518 if (elf_msp430_howto_table[i].name != NULL 215 519 && strcasecmp (elf_msp430_howto_table[i].name, r_name) == 0) 216 520 return &elf_msp430_howto_table[i]; … … msp430_final_link_relocate (reloc_howto_type * howto, bfd * input_bfd, 282 586 { 283 587 bfd_reloc_status_type r = bfd_reloc_ok; 284 588 bfd_vma x; 285 bfd_signed_vma srel ;589 bfd_signed_vma srel = 0; 286 590 287 switch (howto->type)591 if (howto->type > R_MSP430_32 && howto->type < R_MSP430_max) 288 592 { 289 case R_MSP430_10_PCREL:290 593 contents += rel->r_offset; 291 594 srel = (bfd_signed_vma) relocation; 292 595 srel += rel->r_addend; 293 srel -= rel->r_offset; 596 597 if(howto->pc_relative) 598 { 599 srel -= rel->r_offset; 600 srel -= (input_section->output_section->vma + 601 input_section->output_offset); 602 } 603 604 switch (howto->type) 605 { 606 case R_MSP430X_PCREL_D: // PC relative dst operand of calla 607 case R_MSP430X_PCREL_INDXD: // 16-bit idx in mova/bra instruction PC relative (symbolic) mode operand 608 srel -= 2; // operand located 2 bytes after opcode 609 break; 610 case R_MSP430X_PCREL_SRC: // PC-relative 20-bit address operand 611 case R_MSP430X_PCREL_SRC_BYTE: 612 case R_MSP430X_PCREL_DST: 613 case R_MSP430X_PCREL_DST_BYTE: 614 srel -= 4; // operand located 4 bytes after opcode 615 break; 616 case R_MSP430X_PCREL_DST_2ND: 617 case R_MSP430X_PCREL_DST_2ND_BYTE: 618 srel -= 6; // operand located 6 bytes after opcode 619 break; 620 } 621 } 622 623 switch (howto->type) 624 { 625 case R_MSP430_10_PCREL: 294 626 srel -= 2; /* Branch instructions add 2 to the PC... */ 295 srel -= (input_section->output_section->vma +296 input_section->output_offset);297 627 298 628 if (srel & 1) 299 629 return bfd_reloc_outofrange; … … msp430_final_link_relocate (reloc_howto_type * howto, bfd * input_bfd, 311 641 break; 312 642 313 643 case R_MSP430_2X_PCREL: 314 contents += rel->r_offset;315 srel = (bfd_signed_vma) relocation;316 srel += rel->r_addend;317 srel -= rel->r_offset;318 644 srel -= 2; /* Branch instructions add 2 to the PC... */ 319 srel -= (input_section->output_section->vma +320 input_section->output_offset);321 645 322 646 if (srel & 1) 323 647 return bfd_reloc_outofrange; … … msp430_final_link_relocate (reloc_howto_type * howto, bfd * input_bfd, 341 665 342 666 case R_MSP430_16_PCREL: 343 667 case R_MSP430_RL_PCREL: 344 contents += rel->r_offset;345 srel = (bfd_signed_vma) relocation;346 srel += rel->r_addend;347 srel -= rel->r_offset;348 668 /* Only branch instructions add 2 to the PC... */ 349 srel -= (input_section->output_section->vma +350 input_section->output_offset);351 669 352 670 if (srel & 1) 353 671 return bfd_reloc_outofrange; … … msp430_final_link_relocate (reloc_howto_type * howto, bfd * input_bfd, 356 674 break; 357 675 358 676 case R_MSP430_16_PCREL_BYTE: 359 contents += rel->r_offset;360 srel = (bfd_signed_vma) relocation;361 srel += rel->r_addend;362 srel -= rel->r_offset;363 677 /* Only branch instructions add 2 to the PC... */ 364 srel -= (input_section->output_section->vma +365 input_section->output_offset);366 678 367 679 bfd_put_16 (input_bfd, srel & 0xffff, contents); 368 680 break; 369 681 370 682 case R_MSP430_16_BYTE: 371 contents += rel->r_offset;372 srel = (bfd_signed_vma) relocation;373 srel += rel->r_addend;374 683 bfd_put_16 (input_bfd, srel & 0xffff, contents); 375 684 break; 376 685 377 686 case R_MSP430_16: 378 contents += rel->r_offset;379 srel = (bfd_signed_vma) relocation;380 srel += rel->r_addend;381 382 687 if (srel & 1) 383 688 return bfd_reloc_notsupported; 384 689 385 690 bfd_put_16 (input_bfd, srel & 0xffff, contents); 386 691 break; 387 692 693 case R_MSP430X_SRC: // address operand 694 case R_MSP430X_PCREL_SRC: // PC-relative address operand 695 696 // 20 bit reloc for msp430x 697 // src in Non-register mode extended instructions, 698 // imm/abs in bra instruction 699 700 // src(19:16) located at positions 10:7 of extension word 701 // src(15:0) located just after opcode 702 703 if (srel & 1) // odd address 704 return bfd_reloc_notsupported; 705 /* and fall trough, no break here!!! */ 706 case R_MSP430X_SRC_BYTE: // byte instructions or immediate operand 707 case R_MSP430X_PCREL_SRC_BYTE: 708 x = bfd_get_16 (input_bfd, contents); 709 /* 4 most-significant bits */ 710 x = (x & 0xf87f) | ((srel >> 9) & 0x0780); 711 bfd_put_16 (input_bfd, x, contents); 712 /* 16 least-significant bits */ 713 bfd_put_16 (input_bfd, srel & 0xffff, contents + 4); 714 break; 715 716 case R_MSP430X_DST: // address operand 717 case R_MSP430X_PCREL_DST: 718 719 // 20 bit reloc for msp430x 720 // dst in Non-register mode extended instructions, 721 // imm/abs/20-bit idx in calla instruction 722 723 // dst(19:16) located at positions 3:0 of extension word 724 // dst(15:0) located just after opcode 725 726 if (srel & 1) // odd address 727 return bfd_reloc_notsupported; 728 /* and fall trough, no break here!!! */ 729 case R_MSP430X_DST_BYTE: // byte instructions or immediate operand 730 case R_MSP430X_PCREL_DST_BYTE: 731 x = bfd_get_16 (input_bfd, contents); 732 /* 4 most-significant bits */ 733 x = (x & 0xfff0) | ((srel >> 16) & 0x000f); 734 bfd_put_16 (input_bfd, x, contents); 735 /* 16 least-significant bits */ 736 bfd_put_16 (input_bfd, srel & 0xffff, contents + 4); 737 break; 738 739 case R_MSP430X_DST_2ND: // address operand 740 case R_MSP430X_PCREL_DST_2ND: 741 742 // 20 bit reloc for msp430x 743 // dst in Non-register mode extended instructions, 744 745 // dst(19:16) located at positions 3:0 of extension word 746 // dst(15:0) located after src(15:0) 747 748 if (srel & 1) // odd address 749 return bfd_reloc_notsupported; 750 /* and fall trough, no break here!!! */ 751 case R_MSP430X_DST_2ND_BYTE: // byte instructions or immediate operand 752 case R_MSP430X_PCREL_DST_2ND_BYTE: 753 x = bfd_get_16 (input_bfd, contents); 754 /* 4 most-significant bits */ 755 x = (x & 0xfff0) | ((srel >> 16) & 0x000f); 756 bfd_put_16 (input_bfd, x, contents); 757 /* 16 least-significant bits */ 758 bfd_put_16 (input_bfd, srel & 0xffff, contents + 6); 759 break; 760 761 case R_MSP430X_S: // absolute src operand of address instructions 762 // 20 bit reloc for msp430x 763 764 // src(19:16) located at positions 11:8 of opcode 765 // src(15:0) located just after opcode 766 767 if (srel & 1) //odd address 768 return bfd_reloc_notsupported; 769 /* and fall trough, no break here!!! */ 770 case R_MSP430X_S_BYTE: // immediate src operand of address instructions 771 x = bfd_get_16 (input_bfd, contents); 772 /* 4 most-significant bits */ 773 x = (x & 0xf0ff) | ((srel >> 8) & 0x0f00); 774 bfd_put_16 (input_bfd, x, contents); 775 /* 16 least-significant bits */ 776 bfd_put_16 (input_bfd, srel & 0xffff, contents + 2); 777 break; 778 779 case R_MSP430X_D: // absolute dst operand of address instructions 780 case R_MSP430X_PCREL_D: // PC relative dst operand of calla 781 // 20 bit reloc for msp430x, 782 783 // dst(19:16) located at positions 3:0 of opcode 784 // dst(15:0) located just after opcode 785 786 if (srel & 1) //odd address 787 return bfd_reloc_notsupported; 788 /* and fall trough, no break here!!! */ 789 case R_MSP430X_D_BYTE: //immediate dst operand of address instructions 790 791 x = bfd_get_16 (input_bfd, contents); 792 /* 4 most-significant bits */ 793 x = (x & 0xfff0) | ((srel >> 16) & 0x000f); 794 bfd_put_16 (input_bfd, x, contents); 795 /* 16 least-significant bits */ 796 bfd_put_16 (input_bfd, srel & 0xffff, contents + 2); 797 break; 798 799 case R_MSP430X_PCREL_INDXD: // 16-bit idx in mova/bra instruction PC relative (symbolic) mode operand 800 801 if (srel & 1) //odd address 802 return bfd_reloc_notsupported; 803 case R_MSP430X_INDXD: // 16-bit idx in calla/mova/bra instruction 804 805 x = srel & 0xffff; 806 bfd_put_16 (input_bfd, x, contents + 2); //16 least-significant bits 807 break; 808 388 809 default: 389 810 r = _bfd_final_link_relocate (howto, input_bfd, input_section, 390 811 contents, rel->r_offset, … … bfd_elf_msp430_final_write_processing (bfd * abfd, 560 981 val = E_MSP430_MACH_MSP430x16; 561 982 break; 562 983 984 case bfd_mach_msp20: 985 val = E_MSP430_MACH_MSP430x20; 986 break; 987 988 case bfd_mach_msp21: 989 val = E_MSP430_MACH_MSP430x21; 990 break; 991 992 case bfd_mach_msp22: 993 val = E_MSP430_MACH_MSP430x22; 994 break; 995 996 case bfd_mach_msp23: 997 val = E_MSP430_MACH_MSP430x23; 998 break; 999 1000 case bfd_mach_msp24: 1001 val = E_MSP430_MACH_MSP430x24; 1002 break; 1003 1004 case bfd_mach_msp241: 1005 val = E_MSP430_MACH_MSP430x241; 1006 break; 1007 1008 case bfd_mach_msp26: 1009 val = E_MSP430_MACH_MSP430x26; 1010 break; 1011 563 1012 case bfd_mach_msp31: 564 1013 val = E_MSP430_MACH_MSP430x31; 565 1014 break; … … bfd_elf_msp430_final_write_processing (bfd * abfd, 587 1036 case bfd_mach_msp44: 588 1037 val = E_MSP430_MACH_MSP430x44; 589 1038 break; 1039 1040 case bfd_mach_msp46: 1041 val = E_MSP430_MACH_MSP430x46; 1042 break; 1043 1044 case bfd_mach_msp47: 1045 val = E_MSP430_MACH_MSP430x47; 1046 break; 1047 1048 case bfd_mach_msp471: 1049 val = E_MSP430_MACH_MSP430x471; 1050 break; 1051 1052 case bfd_mach_msp54: 1053 val = E_MSP430_MACH_MSP430x54; 1054 break; 590 1055 } 591 1056 592 1057 elf_elfheader (abfd)->e_machine = EM_MSP430; … … elf32_msp430_object_p (bfd * abfd) 637 1102 e_set = bfd_mach_msp16; 638 1103 break; 639 1104 1105 case E_MSP430_MACH_MSP430x20: 1106 e_set = bfd_mach_msp20; 1107 break; 1108 1109 case E_MSP430_MACH_MSP430x21: 1110 e_set = bfd_mach_msp21; 1111 break; 1112 1113 case E_MSP430_MACH_MSP430x22: 1114 e_set = bfd_mach_msp22; 1115 break; 1116 1117 case E_MSP430_MACH_MSP430x23: 1118 e_set = bfd_mach_msp23; 1119 break; 1120 1121 case E_MSP430_MACH_MSP430x24: 1122 e_set = bfd_mach_msp24; 1123 break; 1124 1125 case E_MSP430_MACH_MSP430x241: 1126 e_set = bfd_mach_msp241; 1127 break; 1128 1129 case E_MSP430_MACH_MSP430x26: 1130 e_set = bfd_mach_msp26; 1131 break; 1132 640 1133 case E_MSP430_MACH_MSP430x31: 641 1134 e_set = bfd_mach_msp31; 642 1135 break; … … elf32_msp430_object_p (bfd * abfd) 664 1157 case E_MSP430_MACH_MSP430x44: 665 1158 e_set = bfd_mach_msp44; 666 1159 break; 1160 1161 case E_MSP430_MACH_MSP430x46: 1162 e_set = bfd_mach_msp46; 1163 break; 1164 1165 case E_MSP430_MACH_MSP430x47: 1166 e_set = bfd_mach_msp47; 1167 break; 1168 1169 case E_MSP430_MACH_MSP430x471: 1170 e_set = bfd_mach_msp471; 1171 break; 1172 1173 case E_MSP430_MACH_MSP430x54: 1174 e_set = bfd_mach_msp54; 1175 break; 667 1176 } 668 1177 } 669 1178 -
binutils-2.20.1
diff --git binutils-2.20.1.orig/bfd/libbfd.h binutils-2.20.1/bfd/libbfd.h index 2450b2d..5c8e0e9 100644
old new static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", 2004 2004 "BFD_RELOC_MSP430_16_BYTE", 2005 2005 "BFD_RELOC_MSP430_2X_PCREL", 2006 2006 "BFD_RELOC_MSP430_RL_PCREL", 2007 "BFD_RELOC_MSP430X_SRC_BYTE", 2008 "BFD_RELOC_MSP430X_SRC", 2009 "BFD_RELOC_MSP430X_DST_BYTE", 2010 "BFD_RELOC_MSP430X_DST", 2011 "BFD_RELOC_MSP430X_DST_2ND_BYTE", 2012 "BFD_RELOC_MSP430X_DST_2ND", 2013 "BFD_RELOC_MSP430X_PCREL_SRC_BYTE", 2014 "BFD_RELOC_MSP430X_PCREL_SRC", 2015 "BFD_RELOC_MSP430X_PCREL_DST_BYTE", 2016 "BFD_RELOC_MSP430X_PCREL_DST", 2017 "BFD_RELOC_MSP430X_PCREL_DST_2ND", 2018 "BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE", 2019 "BFD_RELOC_MSP430X_S_BYTE", 2020 "BFD_RELOC_MSP430X_S", 2021 "BFD_RELOC_MSP430X_D_BYTE", 2022 "BFD_RELOC_MSP430X_D", 2023 "BFD_RELOC_MSP430X_PCREL_D", 2024 "BFD_RELOC_MSP430X_INDXD", 2025 "BFD_RELOC_MSP430X_PCREL_INDXD", 2007 2026 "BFD_RELOC_IQ2000_OFFSET_16", 2008 2027 "BFD_RELOC_IQ2000_OFFSET_21", 2009 2028 "BFD_RELOC_IQ2000_UHI16", -
binutils-2.20.1
diff --git binutils-2.20.1.orig/bfd/reloc.c binutils-2.20.1/bfd/reloc.c index 3be29fe..9375f8e 100644
old new ENUMX 4993 4993 BFD_RELOC_MSP430_2X_PCREL 4994 4994 ENUMX 4995 4995 BFD_RELOC_MSP430_RL_PCREL 4996 ENUMX 4997 BFD_RELOC_MSP430X_SRC_BYTE 4998 ENUMX 4999 BFD_RELOC_MSP430X_SRC 5000 ENUMX 5001 BFD_RELOC_MSP430X_DST_BYTE 5002 ENUMX 5003 BFD_RELOC_MSP430X_DST 5004 ENUMX 5005 BFD_RELOC_MSP430X_DST_2ND_BYTE 5006 ENUMX 5007 BFD_RELOC_MSP430X_DST_2ND 5008 ENUMX 5009 BFD_RELOC_MSP430X_PCREL_SRC_BYTE 5010 ENUMX 5011 BFD_RELOC_MSP430X_PCREL_SRC 5012 ENUMX 5013 BFD_RELOC_MSP430X_PCREL_DST_BYTE 5014 ENUMX 5015 BFD_RELOC_MSP430X_PCREL_DST 5016 ENUMX 5017 BFD_RELOC_MSP430X_PCREL_DST_2ND 5018 ENUMX 5019 BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE 5020 ENUMX 5021 BFD_RELOC_MSP430X_S_BYTE 5022 ENUMX 5023 BFD_RELOC_MSP430X_S 5024 ENUMX 5025 BFD_RELOC_MSP430X_D_BYTE 5026 ENUMX 5027 BFD_RELOC_MSP430X_D 5028 ENUMX 5029 BFD_RELOC_MSP430X_PCREL_D 5030 ENUMX 5031 BFD_RELOC_MSP430X_INDXD 5032 ENUMX 5033 BFD_RELOC_MSP430X_PCREL_INDXD 4996 5034 ENUMDOC 4997 5035 msp430 specific relocation codes 4998 5036 -
gas/config/tc-msp430.c
diff --git binutils-2.20.1.orig/gas/config/tc-msp430.c binutils-2.20.1/gas/config/tc-msp430.c index 0ccf4db..4784c05 100644
old new 23 23 24 24 #include <limits.h> 25 25 26 #define PUSH_1X_WORKAROUND27 26 #include "as.h" 28 27 #include "subsegs.h" 29 28 #include "opcode/msp430.h" … … 69 68 70 69 int msp430_enable_relax; 71 70 int msp430_enable_polys; 71 int msp430x_repeats; // It's not a right way to use global variable, but I don't know other way how to do it 72 72 73 73 /* GCC uses the some condition codes which we'll 74 74 implement as new polymorph instructions. … … int msp430_enable_polys; 99 99 Also, we add 'jump' instruction: 100 100 jump UNCOND -> jmp br lab 101 101 102 They will have fmt == 4, and insn_opnumb == number of instruction. */ 102 They will have opcode_format() == FMT_EMULATED_POLYMORPH_JUMP, 103 and opcode_variant() == number of instruction. */ 103 104 104 105 struct rcodes_s 105 106 { 106 107 char * name; 107 int index; /* Corresponding insn_opnumb. */108 int index; /* Corresponding opcode_variant(). */ 108 109 int sop; /* Opcode if jump length is short. */ 109 110 long lpos; /* Label position. */ 110 111 long lop0; /* Opcode 1 _word_ (16 bits). */ … … static struct rcodes_s msp430_rcodes[] = 143 144 struct hcodes_s 144 145 { 145 146 char * name; 146 int index; /* Corresponding insn_opnumb. */147 int index; /* Corresponding opcode_variant(). */ 147 148 int tlab; /* Number of labels in short mode. */ 148 149 int op0; /* Opcode for first word of short jump. */ 149 150 int op1; /* Opcode for second word of short jump. */ … … struct mcu_type_s 237 238 int mach; 238 239 }; 239 240 240 #define MSP430_ISA_11 11 241 #define MSP430_ISA_110 110 242 #define MSP430_ISA_12 12 243 #define MSP430_ISA_13 13 244 #define MSP430_ISA_14 14 245 #define MSP430_ISA_15 15 246 #define MSP430_ISA_16 16 247 #define MSP430_ISA_21 21 248 #define MSP430_ISA_31 31 249 #define MSP430_ISA_32 32 250 #define MSP430_ISA_33 33 251 #define MSP430_ISA_41 41 252 #define MSP430_ISA_42 42 253 #define MSP430_ISA_43 43 254 #define MSP430_ISA_44 44 255 256 #define CHECK_RELOC_MSP430 ((imm_op || byte_op)?BFD_RELOC_MSP430_16_BYTE:BFD_RELOC_MSP430_16) 257 #define CHECK_RELOC_MSP430_PCREL ((imm_op || byte_op)?BFD_RELOC_MSP430_16_PCREL_BYTE:BFD_RELOC_MSP430_16_PCREL) 258 259 static struct mcu_type_s mcu_types[] = 241 enum 260 242 { 261 {"msp1", MSP430_ISA_11, bfd_mach_msp11}, 262 {"msp2", MSP430_ISA_14, bfd_mach_msp14}, 263 {"msp430x110", MSP430_ISA_11, bfd_mach_msp11}, 264 {"msp430x112", MSP430_ISA_11, bfd_mach_msp11}, 265 {"msp430x1101", MSP430_ISA_110, bfd_mach_msp110}, 266 {"msp430x1111", MSP430_ISA_110, bfd_mach_msp110}, 267 {"msp430x1121", MSP430_ISA_110, bfd_mach_msp110}, 268 {"msp430x1122", MSP430_ISA_11, bfd_mach_msp110}, 269 {"msp430x1132", MSP430_ISA_11, bfd_mach_msp110}, 270 271 {"msp430x122", MSP430_ISA_12, bfd_mach_msp12}, 272 {"msp430x123", MSP430_ISA_12, bfd_mach_msp12}, 273 {"msp430x1222", MSP430_ISA_12, bfd_mach_msp12}, 274 {"msp430x1232", MSP430_ISA_12, bfd_mach_msp12}, 275 276 {"msp430x133", MSP430_ISA_13, bfd_mach_msp13}, 277 {"msp430x135", MSP430_ISA_13, bfd_mach_msp13}, 278 {"msp430x1331", MSP430_ISA_13, bfd_mach_msp13}, 279 {"msp430x1351", MSP430_ISA_13, bfd_mach_msp13}, 280 {"msp430x147", MSP430_ISA_14, bfd_mach_msp14}, 281 {"msp430x148", MSP430_ISA_14, bfd_mach_msp14}, 282 {"msp430x149", MSP430_ISA_14, bfd_mach_msp14}, 283 284 {"msp430x155", MSP430_ISA_15, bfd_mach_msp15}, 285 {"msp430x156", MSP430_ISA_15, bfd_mach_msp15}, 286 {"msp430x157", MSP430_ISA_15, bfd_mach_msp15}, 287 {"msp430x167", MSP430_ISA_16, bfd_mach_msp16}, 288 {"msp430x168", MSP430_ISA_16, bfd_mach_msp16}, 289 {"msp430x169", MSP430_ISA_16, bfd_mach_msp16}, 290 {"msp430x1610", MSP430_ISA_16, bfd_mach_msp16}, 291 {"msp430x1611", MSP430_ISA_16, bfd_mach_msp16}, 292 {"msp430x1612", MSP430_ISA_16, bfd_mach_msp16}, 293 294 {"msp430x2101", MSP430_ISA_21, bfd_mach_msp21}, 295 {"msp430x2111", MSP430_ISA_21, bfd_mach_msp21}, 296 {"msp430x2121", MSP430_ISA_21, bfd_mach_msp21}, 297 {"msp430x2131", MSP430_ISA_21, bfd_mach_msp21}, 243 CORE_MASK = 0x3, 244 CPU4_BUG = 1 << 2, // push #4, push #8 cannot use CG 245 CPU7_BUG = 1 << 3, // CALL and PUSH with @SP+, @SP, and X(SP) uses the SP to calculate the address, then decrements it 246 CPU8_BUG = 1 << 4, // using odd values with SP 247 CPU11_BUG = 1 << 5, // When addressing the program counter (PC) in register mode and the PC is the destination, the 248 // status register (SR) may be erroneous. The instructions BIS, BIC, and MOV do not affect SR contents. 249 CPU12_BUG = 1 << 6, // Any instruction immediately following a CMP(.B) or BIT(.B) instruction where the PC is the 250 // destination address using register mode is ignored or erroneously executed. 251 // *** we can issue warning if any instruction other than nop follows cmp(.b) or bit(.b) *** 252 CPU13_BUG = 1 << 7, // Performing arithmetic operations with the status register as the destination address does not 253 // update the status register as intended. The result in SR can be invalid, leading to erroneous low- 254 // power mode entry. *** we can issue warning *** 255 CPU16_BUG = 1 << 8, // With indexed addressing mode and instructions calla, mova and bra 256 // it is not possible to reach memory above 64k if the register content is <64k. 257 }; 258 static core_t msp430_core( struct mcu_type_s const * mcu ) 259 { 260 return (core_t)(mcu->isa & CORE_MASK); 261 } 262 263 #define MSP430_ISA_11 (CORE_430 | CPU4_BUG) 264 #define MSP430_ISA_110 (CORE_430 | CPU4_BUG) 265 #define MSP430_ISA_12 (CORE_430 | CPU4_BUG) 266 #define MSP430_ISA_13 (CORE_430 | CPU4_BUG) 267 #define MSP430_ISA_14 (CORE_430 | CPU4_BUG) 268 #define MSP430_ISA_15 (CORE_430 | CPU4_BUG) 269 #define MSP430_ISA_16 (CORE_430 | CPU4_BUG) 270 #define MSP430_ISA_20 (CORE_430 | CPU4_BUG) 271 #define MSP430_ISA_21 (CORE_430 | CPU4_BUG) 272 #define MSP430_ISA_21x1 (CORE_430 | CPU4_BUG|CPU11_BUG|CPU12_BUG|CPU13_BUG) 273 #define MSP430_ISA_22 (CORE_430) 274 #define MSP430_ISA_23 (CORE_430) 275 #define MSP430_ISA_24 (CORE_430 | CPU8_BUG) 276 #define MSP430_ISA_241 (CORE_430X | CPU7_BUG|CPU8_BUG|CPU16_BUG) 277 #define MSP430_ISA_26 (CORE_430X | CPU7_BUG|CPU8_BUG|CPU16_BUG) 278 #define MSP430_ISA_31 (CORE_430 | CPU4_BUG) 279 #define MSP430_ISA_32 (CORE_430 | CPU4_BUG) 280 #define MSP430_ISA_33 (CORE_430 | CPU4_BUG) 281 #define MSP430_ISA_41 (CORE_430 | CPU4_BUG) 282 #define MSP430_ISA_42 (CORE_430 | CPU4_BUG) 283 #define MSP430_ISA_43 (CORE_430 | CPU4_BUG) 284 #define MSP430_ISA_44 (CORE_430 | CPU4_BUG) 285 #define MSP430_ISA_46 (CORE_430X | CPU7_BUG|CPU8_BUG) 286 #define MSP430_ISA_47 (CORE_430) 287 #define MSP430_ISA_471 (CORE_430X) 288 #define MSP430_ISA_54 (CORE_430X2) 289 290 #define CHECK_RELOC_MSP430 ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16) 291 #define CHECK_RELOC_MSP430_PCREL ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430_16_PCREL_BYTE : BFD_RELOC_MSP430_16_PCREL) 292 #define CHECK_RELOC_MSP430X_SRC ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430X_SRC_BYTE : BFD_RELOC_MSP430X_SRC) 293 #define CHECK_RELOC_MSP430X_PCREL_SRC ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430X_PCREL_SRC_BYTE : BFD_RELOC_MSP430X_PCREL_SRC) 294 #define CHECK_RELOC_MSP430X_DST ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430X_DST_BYTE : BFD_RELOC_MSP430X_DST) 295 #define CHECK_RELOC_MSP430X_PCREL_DST ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430X_PCREL_DST_BYTE : BFD_RELOC_MSP430X_PCREL_DST) 296 #define CHECK_RELOC_MSP430X_DST_2ND ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430X_DST_2ND_BYTE : BFD_RELOC_MSP430X_DST_2ND) 297 #define CHECK_RELOC_MSP430X_PCREL_DST_2ND ((imm_op || op_width == BYTE_OP) ? BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE : BFD_RELOC_MSP430X_PCREL_DST_2ND) 298 299 static struct mcu_type_s const mcu_types[] = 300 { 301 {"msp1", MSP430_ISA_11, bfd_mach_msp11}, 302 {"msp2", MSP430_ISA_14, bfd_mach_msp14}, 303 {"msp3", MSP430_ISA_46, bfd_mach_msp46}, 304 {"msp4", MSP430_ISA_47, bfd_mach_msp47}, 305 {"msp5", MSP430_ISA_471, bfd_mach_msp471}, 306 {"msp6", MSP430_ISA_54, bfd_mach_msp54}, 307 {"msp430x110", MSP430_ISA_11, bfd_mach_msp11}, 308 {"msp430x112", MSP430_ISA_11, bfd_mach_msp11}, 309 {"msp430x1101", MSP430_ISA_110, bfd_mach_msp110}, 310 {"msp430x1111", MSP430_ISA_110, bfd_mach_msp110}, 311 {"msp430x1121", MSP430_ISA_110, bfd_mach_msp110}, 312 {"msp430x1122", MSP430_ISA_11, bfd_mach_msp110}, 313 {"msp430x1132", MSP430_ISA_11, bfd_mach_msp110}, 314 315 {"msp430x122", MSP430_ISA_12, bfd_mach_msp12}, 316 {"msp430x123", MSP430_ISA_12, bfd_mach_msp12}, 317 {"msp430x1222", MSP430_ISA_12, bfd_mach_msp12}, 318 {"msp430x1232", MSP430_ISA_12, bfd_mach_msp12}, 319 320 {"msp430x133", MSP430_ISA_13, bfd_mach_msp13}, 321 {"msp430x135", MSP430_ISA_13, bfd_mach_msp13}, 322 {"msp430x1331", MSP430_ISA_13, bfd_mach_msp13}, 323 {"msp430x1351", MSP430_ISA_13, bfd_mach_msp13}, 324 {"msp430x147", MSP430_ISA_14, bfd_mach_msp14}, 325 {"msp430x148", MSP430_ISA_14, bfd_mach_msp14}, 326 {"msp430x149", MSP430_ISA_14, bfd_mach_msp14}, 327 {"msp430x1471", MSP430_ISA_14, bfd_mach_msp14}, 328 {"msp430x1481", MSP430_ISA_14, bfd_mach_msp14}, 329 {"msp430x1491", MSP430_ISA_14, bfd_mach_msp14}, 330 331 {"msp430x155", MSP430_ISA_15, bfd_mach_msp15}, 332 {"msp430x156", MSP430_ISA_15, bfd_mach_msp15}, 333 {"msp430x157", MSP430_ISA_15, bfd_mach_msp15}, 334 {"msp430x167", MSP430_ISA_16, bfd_mach_msp16}, 335 {"msp430x168", MSP430_ISA_16, bfd_mach_msp16}, 336 {"msp430x169", MSP430_ISA_16, bfd_mach_msp16}, 337 {"msp430x1610", MSP430_ISA_16, bfd_mach_msp16}, 338 {"msp430x1611", MSP430_ISA_16, bfd_mach_msp16}, 339 {"msp430x1612", MSP430_ISA_16, bfd_mach_msp16}, 340 341 {"msp430x2001", MSP430_ISA_20, bfd_mach_msp20}, 342 {"msp430x2011", MSP430_ISA_20, bfd_mach_msp20}, 343 344 {"msp430x2002", MSP430_ISA_20, bfd_mach_msp20}, 345 {"msp430x2012", MSP430_ISA_20, bfd_mach_msp20}, 346 347 {"msp430x2003", MSP430_ISA_20, bfd_mach_msp20}, 348 {"msp430x2013", MSP430_ISA_20, bfd_mach_msp20}, 349 350 {"msp430x2101", MSP430_ISA_21x1, bfd_mach_msp21}, 351 {"msp430x2111", MSP430_ISA_21x1, bfd_mach_msp21}, 352 {"msp430x2112", MSP430_ISA_21, bfd_mach_msp21}, 353 {"msp430x2121", MSP430_ISA_21x1, bfd_mach_msp21}, 354 {"msp430x2122", MSP430_ISA_21, bfd_mach_msp21}, 355 {"msp430x2131", MSP430_ISA_21x1, bfd_mach_msp21}, 356 {"msp430x2132", MSP430_ISA_21, bfd_mach_msp21}, 357 358 /* 20101114: note that these chips are msp430g22XX, not msp430f22XX. 359 * There are no msp430f22XX with these familty codes. Historically, 360 * the F-type chips are not compatible with the G-type chips in 361 * terms of flash size and address. Since gcc does not distinguish 362 * chips by memory type (uses x instead of f or g), other chips 363 * cannot be supported. */ 364 {"msp430x2201", MSP430_ISA_22, bfd_mach_msp22}, // VALUE-LINUE msp430g 365 {"msp430x2211", MSP430_ISA_22, bfd_mach_msp22}, // VALUE-LINUE msp430g 366 {"msp430x2221", MSP430_ISA_22, bfd_mach_msp22}, // VALUE-LINUE msp430g 367 {"msp430x2231", MSP430_ISA_22, bfd_mach_msp22}, // VALUE-LINUE msp430g 368 369 {"msp430x2232", MSP430_ISA_22, bfd_mach_msp22}, 370 {"msp430x2234", MSP430_ISA_22, bfd_mach_msp22}, 371 {"msp430x2252", MSP430_ISA_22, bfd_mach_msp22}, 372 {"msp430x2254", MSP430_ISA_22, bfd_mach_msp22}, 373 {"msp430x2272", MSP430_ISA_22, bfd_mach_msp22}, 374 {"msp430x2274", MSP430_ISA_22, bfd_mach_msp22}, 375 376 {"msp430x233", MSP430_ISA_24, bfd_mach_msp24}, 377 {"msp430x235", MSP430_ISA_24, bfd_mach_msp24}, 378 {"msp430x2330", MSP430_ISA_23, bfd_mach_msp23}, 379 {"msp430x2350", MSP430_ISA_23, bfd_mach_msp23}, 380 {"msp430x2370", MSP430_ISA_23, bfd_mach_msp23}, 381 382 {"msp430x247", MSP430_ISA_24, bfd_mach_msp24}, 383 {"msp430x2471", MSP430_ISA_24, bfd_mach_msp24}, 384 {"msp430x248", MSP430_ISA_24, bfd_mach_msp24}, 385 {"msp430x2481", MSP430_ISA_24, bfd_mach_msp24}, 386 {"msp430x249", MSP430_ISA_24, bfd_mach_msp24}, 387 {"msp430x2491", MSP430_ISA_24, bfd_mach_msp24}, 388 {"msp430x2410", MSP430_ISA_24, bfd_mach_msp24}, 389 390 {"msp430x2416", MSP430_ISA_241, bfd_mach_msp241}, 391 {"msp430x2417", MSP430_ISA_241, bfd_mach_msp241}, 392 {"msp430x2418", MSP430_ISA_241, bfd_mach_msp241}, 393 {"msp430x2419", MSP430_ISA_241, bfd_mach_msp241}, 298 394 299 {"msp430x311", MSP430_ISA_31, bfd_mach_msp31}, 300 {"msp430x312", MSP430_ISA_31, bfd_mach_msp31}, 301 {"msp430x313", MSP430_ISA_31, bfd_mach_msp31}, 302 {"msp430x314", MSP430_ISA_31, bfd_mach_msp31}, 303 {"msp430x315", MSP430_ISA_31, bfd_mach_msp31}, 304 {"msp430x323", MSP430_ISA_32, bfd_mach_msp32}, 305 {"msp430x325", MSP430_ISA_32, bfd_mach_msp32}, 306 {"msp430x336", MSP430_ISA_33, bfd_mach_msp33}, 307 {"msp430x337", MSP430_ISA_33, bfd_mach_msp33}, 308 309 {"msp430x412", MSP430_ISA_41, bfd_mach_msp41}, 310 {"msp430x413", MSP430_ISA_41, bfd_mach_msp41}, 311 {"msp430x415", MSP430_ISA_41, bfd_mach_msp41}, 312 {"msp430x417", MSP430_ISA_41, bfd_mach_msp41}, 313 314 {"msp430xE423", MSP430_ISA_42, bfd_mach_msp42}, 315 {"msp430xE425", MSP430_ISA_42, bfd_mach_msp42}, 316 {"msp430xE427", MSP430_ISA_42, bfd_mach_msp42}, 317 318 {"msp430xW423", MSP430_ISA_42, bfd_mach_msp42}, 319 {"msp430xW425", MSP430_ISA_42, bfd_mach_msp42}, 320 {"msp430xW427", MSP430_ISA_42, bfd_mach_msp42}, 321 322 {"msp430xG437", MSP430_ISA_43, bfd_mach_msp43}, 323 {"msp430xG438", MSP430_ISA_43, bfd_mach_msp43}, 324 {"msp430xG439", MSP430_ISA_43, bfd_mach_msp43}, 325 326 {"msp430x435", MSP430_ISA_43, bfd_mach_msp43}, 327 {"msp430x436", MSP430_ISA_43, bfd_mach_msp43}, 328 {"msp430x437", MSP430_ISA_43, bfd_mach_msp43}, 329 {"msp430x447", MSP430_ISA_44, bfd_mach_msp44}, 330 {"msp430x448", MSP430_ISA_44, bfd_mach_msp44}, 331 {"msp430x449", MSP430_ISA_44, bfd_mach_msp44}, 395 {"msp430x2616", MSP430_ISA_26, bfd_mach_msp26}, 396 {"msp430x2617", MSP430_ISA_26, bfd_mach_msp26}, 397 {"msp430x2618", MSP430_ISA_26, bfd_mach_msp26}, 398 {"msp430x2619", MSP430_ISA_26, bfd_mach_msp26}, 399 400 {"msp430x311", MSP430_ISA_31, bfd_mach_msp31}, 401 {"msp430x312", MSP430_ISA_31, bfd_mach_msp31}, 402 {"msp430x313", MSP430_ISA_31, bfd_mach_msp31}, 403 {"msp430x314", MSP430_ISA_31, bfd_mach_msp31}, 404 {"msp430x315", MSP430_ISA_31, bfd_mach_msp31}, 405 {"msp430x323", MSP430_ISA_32, bfd_mach_msp32}, 406 {"msp430x325", MSP430_ISA_32, bfd_mach_msp32}, 407 {"msp430x336", MSP430_ISA_33, bfd_mach_msp33}, 408 {"msp430x337", MSP430_ISA_33, bfd_mach_msp33}, 409 410 {"msp430x412", MSP430_ISA_41, bfd_mach_msp41}, 411 {"msp430x413", MSP430_ISA_41, bfd_mach_msp41}, 412 {"msp430x415", MSP430_ISA_41, bfd_mach_msp41}, 413 {"msp430x417", MSP430_ISA_41, bfd_mach_msp41}, 414 415 {"msp430x423", MSP430_ISA_42, bfd_mach_msp42}, 416 {"msp430x425", MSP430_ISA_42, bfd_mach_msp42}, 417 {"msp430x427", MSP430_ISA_42, bfd_mach_msp42}, 418 419 {"msp430x4250", MSP430_ISA_42, bfd_mach_msp42}, 420 {"msp430x4260", MSP430_ISA_42, bfd_mach_msp42}, 421 {"msp430x4270", MSP430_ISA_42, bfd_mach_msp42}, 422 423 {"msp430xG4250", MSP430_ISA_42, bfd_mach_msp42}, 424 {"msp430xG4260", MSP430_ISA_42, bfd_mach_msp42}, 425 {"msp430xG4270", MSP430_ISA_42, bfd_mach_msp42}, 426 427 {"msp430xE423", MSP430_ISA_42, bfd_mach_msp42}, 428 {"msp430xE4232", MSP430_ISA_42, bfd_mach_msp42}, 429 {"msp430xE4242", MSP430_ISA_42, bfd_mach_msp42}, 430 {"msp430xE4252", MSP430_ISA_42, bfd_mach_msp42}, 431 {"msp430xE425", MSP430_ISA_42, bfd_mach_msp42}, 432 {"msp430xE427", MSP430_ISA_42, bfd_mach_msp42}, 433 {"msp430xE4272", MSP430_ISA_42, bfd_mach_msp42}, 434 435 {"msp430xW423", MSP430_ISA_42, bfd_mach_msp42}, 436 {"msp430xW425", MSP430_ISA_42, bfd_mach_msp42}, 437 {"msp430xW427", MSP430_ISA_42, bfd_mach_msp42}, 438 439 {"msp430xG437", MSP430_ISA_43, bfd_mach_msp43}, 440 {"msp430xG438", MSP430_ISA_43, bfd_mach_msp43}, 441 {"msp430xG439", MSP430_ISA_43, bfd_mach_msp43}, 442 443 {"msp430x435", MSP430_ISA_43, bfd_mach_msp43}, 444 {"msp430x4351", MSP430_ISA_43, bfd_mach_msp43}, 445 {"msp430x436", MSP430_ISA_43, bfd_mach_msp43}, 446 {"msp430x4361", MSP430_ISA_43, bfd_mach_msp43}, 447 {"msp430x437", MSP430_ISA_43, bfd_mach_msp43}, 448 {"msp430x4371", MSP430_ISA_43, bfd_mach_msp43}, 449 {"msp430x447", MSP430_ISA_44, bfd_mach_msp44}, 450 {"msp430x448", MSP430_ISA_44, bfd_mach_msp44}, 451 {"msp430x449", MSP430_ISA_44, bfd_mach_msp44}, 452 453 {"msp430xG4616", MSP430_ISA_46, bfd_mach_msp46}, 454 {"msp430xG4617", MSP430_ISA_46, bfd_mach_msp46}, 455 {"msp430xG4618", MSP430_ISA_46, bfd_mach_msp46}, 456 {"msp430xG4619", MSP430_ISA_46, bfd_mach_msp46}, 457 458 {"msp430x4783", MSP430_ISA_47, bfd_mach_msp47}, 459 {"msp430x4784", MSP430_ISA_47, bfd_mach_msp47}, 460 {"msp430x4793", MSP430_ISA_47, bfd_mach_msp47}, 461 {"msp430x4794", MSP430_ISA_47, bfd_mach_msp47}, 462 463 {"msp430x47166", MSP430_ISA_471, bfd_mach_msp471}, 464 {"msp430x47176", MSP430_ISA_471, bfd_mach_msp471}, 465 {"msp430x47186", MSP430_ISA_471, bfd_mach_msp471}, 466 {"msp430x47196", MSP430_ISA_471, bfd_mach_msp471}, 467 468 {"msp430x47167", MSP430_ISA_471, bfd_mach_msp471}, 469 {"msp430x47177", MSP430_ISA_471, bfd_mach_msp471}, 470 {"msp430x47187", MSP430_ISA_471, bfd_mach_msp471}, 471 {"msp430x47197", MSP430_ISA_471, bfd_mach_msp471}, 472 473 {"msp430x5418", MSP430_ISA_54, bfd_mach_msp54}, 474 {"msp430x5419", MSP430_ISA_54, bfd_mach_msp54}, 475 {"msp430x5435", MSP430_ISA_54, bfd_mach_msp54}, 476 {"msp430x5436", MSP430_ISA_54, bfd_mach_msp54}, 477 {"msp430x5437", MSP430_ISA_54, bfd_mach_msp54}, 478 {"msp430x5438", MSP430_ISA_54, bfd_mach_msp54}, 479 480 {"msp430x5510", MSP430_ISA_54, bfd_mach_msp54}, 481 {"msp430x5513", MSP430_ISA_54, bfd_mach_msp54}, 482 {"msp430x5514", MSP430_ISA_54, bfd_mach_msp54}, 483 {"msp430x5515", MSP430_ISA_54, bfd_mach_msp54}, 484 {"msp430x5517", MSP430_ISA_54, bfd_mach_msp54}, 485 {"msp430x5519", MSP430_ISA_54, bfd_mach_msp54}, 486 {"msp430x5521", MSP430_ISA_54, bfd_mach_msp54}, 487 {"msp430x5522", MSP430_ISA_54, bfd_mach_msp54}, 488 {"msp430x5524", MSP430_ISA_54, bfd_mach_msp54}, 489 {"msp430x5525", MSP430_ISA_54, bfd_mach_msp54}, 490 {"msp430x5526", MSP430_ISA_54, bfd_mach_msp54}, 491 {"msp430x5527", MSP430_ISA_54, bfd_mach_msp54}, 492 {"msp430x5528", MSP430_ISA_54, bfd_mach_msp54}, 493 {"msp430x5529", MSP430_ISA_54, bfd_mach_msp54}, 494 {"msp430x6638", MSP430_ISA_54, bfd_mach_msp54}, 495 496 {"cc430x5133", MSP430_ISA_54, bfd_mach_msp54}, 497 {"cc430x5125", MSP430_ISA_54, bfd_mach_msp54}, 498 {"cc430x6125", MSP430_ISA_54, bfd_mach_msp54}, 499 {"cc430x6135", MSP430_ISA_54, bfd_mach_msp54}, 500 {"cc430x6126", MSP430_ISA_54, bfd_mach_msp54}, 501 {"cc430x5137", MSP430_ISA_54, bfd_mach_msp54}, 502 {"cc430x6127", MSP430_ISA_54, bfd_mach_msp54}, 503 {"cc430x6137", MSP430_ISA_54, bfd_mach_msp54}, 332 504 333 505 {NULL, 0, 0} 334 506 }; 335 507 336 508 337 static struct mcu_type_s default_mcu =509 static struct mcu_type_s const default_mcu = 338 510 { "msp430x11", MSP430_ISA_11, bfd_mach_msp11 }; 339 511 340 static struct mcu_type_s * msp430_mcu = & default_mcu;512 static struct mcu_type_s const * msp430_mcu = & default_mcu; 341 513 342 514 /* Profiling capability: 343 515 It is a performance hit to use gcc's profiling approach for this tiny target. … … pow2value (int y) 446 618 static char * 447 619 parse_exp (char * s, expressionS * op) 448 620 { 621 char * in_save = input_line_pointer; 449 622 input_line_pointer = s; 450 623 expression (op); 624 s = input_line_pointer; 625 input_line_pointer = in_save; 451 626 if (op->X_op == O_absent) 452 627 as_bad (_("missing operand")); 453 return input_line_pointer;628 return s; 454 629 } 455 630 456 631 … … extract_operand (char * from, char * to, int limit) 504 679 *(to + size) = 0; 505 680 del_spaces (to); 506 681 507 from++; 682 if(*from == ',') 683 from++; 508 684 509 685 return from; 510 686 } … … msp430_profiler (int dummy ATTRIBUTE_UNUSED) 549 725 return; 550 726 } 551 727 552 input_line_pointer = extract_operand (input_line_pointer, flags, 32); 728 input_line_pointer = extract_operand (input_line_pointer, flags, 32) 729 + 1; // skip trailing zero 553 730 554 731 while (*flags) 555 732 { … … msp430_profiler (int dummy ATTRIBUTE_UNUSED) 662 839 /* Process like ".word xxx" directive. */ 663 840 parse_exp (str, & exp); 664 841 emit_expr (& exp, 2); 665 input_line_pointer = halt ;842 input_line_pointer = halt + 1; 666 843 } 667 844 668 845 /* Fill the rest with zeros. */ … … md_parse_option (int c, char * arg) 766 943 return 0; 767 944 } 768 945 946 static void 947 msp430_repeat_insn (int dummy ATTRIBUTE_UNUSED); 769 948 770 949 const pseudo_typeS md_pseudo_table[] = 771 950 { 772 951 {"arch", msp430_set_arch, 0}, 773 952 {"profiler", msp430_profiler, 0}, 953 {"rpt", msp430_repeat_insn, 0}, 774 954 {NULL, NULL, 0} 775 955 }; 776 956 … … md_show_usage (FILE * stream) 792 972 fprintf (stream, 793 973 _("MSP430 options:\n" 794 974 " -mmcu=[msp430-name] select microcontroller type\n" 795 " msp430x110 msp430x112\n" 796 " msp430x1101 msp430x1111\n" 797 " msp430x1121 msp430x1122 msp430x1132\n" 798 " msp430x122 msp430x123\n" 799 " msp430x1222 msp430x1232\n" 800 " msp430x133 msp430x135\n" 801 " msp430x1331 msp430x1351\n" 802 " msp430x147 msp430x148 msp430x149\n" 803 " msp430x155 msp430x156 msp430x157\n" 804 " msp430x167 msp430x168 msp430x169\n" 805 " msp430x1610 msp430x1611 msp430x1612\n" 806 " msp430x311 msp430x312 msp430x313 msp430x314 msp430x315\n" 807 " msp430x323 msp430x325\n" 808 " msp430x336 msp430x337\n" 809 " msp430x412 msp430x413 msp430x415 msp430x417\n" 810 " msp430xE423 msp430xE425 msp430E427\n" 811 " msp430xW423 msp430xW425 msp430W427\n" 812 " msp430xG437 msp430xG438 msp430G439\n" 813 " msp430x435 msp430x436 msp430x437\n" 814 " msp430x447 msp430x448 msp430x449\n")); 975 " msp430x110 msp430x112\n" 976 " msp430x1101 msp430x1111 msp430x1121\n" 977 " msp430x1122 msp430x1132\n" 978 " msp430x122 msp430x123\n" 979 " msp430x1222 msp430x1232\n" 980 " msp430x133 msp430x135\n" 981 " msp430x1331 msp430x1351\n" 982 " msp430x147 msp430x148 msp430x149\n" 983 " msp430x1471 msp430x1481 msp430x1491\n" 984 " msp430x155 msp430x156 msp430x157\n" 985 " msp430x167 msp430x168 msp430x169\n" 986 " msp430x1610 msp430x1611 msp430x1612\n" 987 " msp430x2001 msp430x2011\n" 988 " msp430x2002 msp430x2012\n" 989 " msp430x2003 msp430x2013\n" 990 " msp430x2101 msp430x2111 msp430x2121 msp430x2131\n" 991 " msp430x2112 msp430x2122 msp430x2132\n" 992 " msp430x2232 msp430x2252 msp430x2272\n" 993 " msp430x2234 msp430x2254 msp430x2274\n" 994 " msp430x233 msp430x235\n" 995 " msp430x2330 msp430x2350 msp430x2370\n" 996 " msp430x247 msp430x248 msp430x249 msp430x2410\n" 997 " msp430x2471 msp430x2481 msp430x2491\n" 998 " msp430x2416 msp430x2417 msp430x2418 msp430x2419\n" 999 " msp430x2616 msp430x2617 msp430x2618 msp430x2619\n" 1000 " msp430x311 msp430x312 msp430x313 msp430x314 msp430x315\n" 1001 " msp430x323 msp430x325\n" 1002 " msp430x336 msp430x337\n" 1003 " msp430x412 msp430x413 msp430x415 msp430x417\n" 1004 " msp430x423 msp430x425 msp430427\n" 1005 " msp430x4250 msp430x4260 msp4304270\n" 1006 " msp430xE423 msp430xE425 msp430E427\n" 1007 " msp430xE4232 msp430xE4242 msp430xE4252 msp430E4272\n" 1008 " msp430xW423 msp430xW425 msp430W427\n" 1009 " msp430xG4250 msp430xG4260 msp430G4270\n" 1010 " msp430xG437 msp430xG438 msp430G439\n" 1011 " msp430x435 msp430x436 msp430x437\n" 1012 " msp430x4351 msp430x4361 msp430x4371\n" 1013 " msp430x447 msp430x448 msp430x449\n" 1014 " msp430xG4616 msp430xG4617 msp430xG4618 msp430xG4619\n" 1015 " msp430x4783 msp430x4784 msp430x4793 msp430x4794\n" 1016 " msp430x47166 msp430x47176 msp430x47186 msp430x47196\n" 1017 " msp430x47167 msp430x47177 msp430x47187 msp430x47197\n" 1018 " msp430x5418 msp430xG5419\n" 1019 " msp430x5435 msp430x5436 msp430x5437 msp430x5438\n" 1020 " cc430x5133\n" 1021 " cc430x5125 cc430x6125 cc430x6135\n" 1022 " cc430x6126\n" 1023 " cc430x5137 cc430x6127 cc430x6137\n" 1024 1025 )); 815 1026 fprintf (stream, 816 1027 _(" -mQ - enable relaxation at assembly time. DANGEROUS!\n" 817 1028 " -mP - enable polymorph instructions\n")); … … md_atof (int type, char * litP, int * sizeP) 851 1062 void 852 1063 md_begin (void) 853 1064 { 854 struct msp430_opcode_s * opcode;1065 struct msp430_opcode_s const * opcode; 855 1066 msp430_hash = hash_new (); 856 1067 857 1068 for (opcode = msp430_opcodes; opcode->name; opcode++) … … check_reg (char * t) 881 1092 return 0; 882 1093 } 883 1094 1095 static void 1096 msp430_substitute_CG(struct msp430_operand_s * op, int workaround) 1097 { 1098 /* Substitute register mode with a constant generator if applicable. */ 1099 if( op->mode != OP_EXP || ( op->exp.X_op != O_constant && op->exp.X_op != O_big )) 1100 return; 1101 if( op->am != 3 || op->reg != 0 ) // not #N 1102 return; 1103 int x = (short) op->exp.X_add_number; /* Extend sign. */ 1104 1105 if (x == 0) 1106 { 1107 op->reg = 3; 1108 op->am = 0; 1109 op->ol = 0; 1110 op->mode = OP_REG; 1111 } 1112 else if (x == 1) 1113 { 1114 op->reg = 3; 1115 op->am = 1; 1116 op->ol = 0; 1117 op->mode = OP_REG; 1118 } 1119 else if (x == 2) 1120 { 1121 op->reg = 3; 1122 op->am = 2; 1123 op->ol = 0; 1124 op->mode = OP_REG; 1125 } 1126 else if (x == -1) 1127 { 1128 op->reg = 3; 1129 op->am = 3; 1130 op->ol = 0; 1131 op->mode = OP_REG; 1132 } 1133 else if (x == 4 && !workaround) 1134 { 1135 op->reg = 2; 1136 op->am = 2; 1137 op->ol = 0; 1138 op->mode = OP_REG; 1139 } 1140 else if (x == 8 && ! workaround) 1141 { 1142 op->reg = 2; 1143 op->am = 3; 1144 op->ol = 0; 1145 op->mode = OP_REG; 1146 } 1147 } 884 1148 885 1149 static int 886 1150 msp430_srcoperand (struct msp430_operand_s * op, 887 char * l, int bin, int * imm_op)1151 char * l, int * imm_op, int imm_min, int imm_max) 888 1152 { 889 1153 char *__tl = l; 890 1154 … … msp430_srcoperand (struct msp430_operand_s * op, 965 1229 x = op->exp.X_add_number; 966 1230 } 967 1231 968 if (op->exp.X_add_number > 65535 || op->exp.X_add_number < -32768)969 970 as_bad (_("value %d out of range. Use #lo() or #hi()"), x);1232 if (x >= imm_max || x < imm_min) 1233 { 1234 as_bad (_("value %d out of %d...%d (0x%X...0x%X) range."), x, imm_min, imm_max - 1, imm_min, imm_max - 1); 971 1235 return 1; 972 1236 } 973 974 /* Now check constants. */975 /* Substitute register mode with a constant generator if applicable. */976 977 x = (short) x; /* Extend sign. */978 979 if (x == 0)980 {981 op->reg = 3;982 op->am = 0;983 op->ol = 0;984 op->mode = OP_REG;985 }986 else if (x == 1)987 {988 op->reg = 3;989 op->am = 1;990 op->ol = 0;991 op->mode = OP_REG;992 }993 else if (x == 2)994 {995 op->reg = 3;996 op->am = 2;997 op->ol = 0;998 op->mode = OP_REG;999 }1000 else if (x == -1)1001 {1002 op->reg = 3;1003 op->am = 3;1004 op->ol = 0;1005 op->mode = OP_REG;1006 }1007 else if (x == 4)1008 {1009 #ifdef PUSH_1X_WORKAROUND1010 if (bin == 0x1200)1011 {1012 /* Remove warning as confusing.1013 as_warn (_("Hardware push bug workaround")); */1014 }1015 else1016 #endif1017 {1018 op->reg = 2;1019 op->am = 2;1020 op->ol = 0;1021 op->mode = OP_REG;1022 }1023 }1024 else if (x == 8)1025 {1026 #ifdef PUSH_1X_WORKAROUND1027 if (bin == 0x1200)1028 {1029 /* Remove warning as confusing.1030 as_warn (_("Hardware push bug workaround")); */1031 }1032 else1033 #endif1034 {1035 op->reg = 2;1036 op->am = 3;1037 op->ol = 0;1038 op->mode = OP_REG;1039 }1040 }1041 1237 } 1042 1238 else if (op->exp.X_op == O_symbol) 1043 1239 { … … msp430_srcoperand (struct msp430_operand_s * op, 1045 1241 } 1046 1242 else if (op->exp.X_op == O_big) 1047 1243 { 1048 short x;1049 1244 if (vshift != -1) 1050 1245 { 1051 1246 op->exp.X_op = O_constant; 1052 1247 op->exp.X_add_number = 0xffff & generic_bignum[vshift]; 1053 x = op->exp.X_add_number;1054 1248 } 1055 1249 else 1056 1250 { … … msp430_srcoperand (struct msp430_operand_s * op, 1059 1253 l); 1060 1254 return 1; 1061 1255 } 1062 1063 if (x == 0)1064 {1065 op->reg = 3;1066 op->am = 0;1067 op->ol = 0;1068 op->mode = OP_REG;1069 }1070 else if (x == 1)1071 {1072 op->reg = 3;1073 op->am = 1;1074 op->ol = 0;1075 op->mode = OP_REG;1076 }1077 else if (x == 2)1078 {1079 op->reg = 3;1080 op->am = 2;1081 op->ol = 0;1082 op->mode = OP_REG;1083 }1084 else if (x == -1)1085 {1086 op->reg = 3;1087 op->am = 3;1088 op->ol = 0;1089 op->mode = OP_REG;1090 }1091 else if (x == 4)1092 {1093 op->reg = 2;1094 op->am = 2;1095 op->ol = 0;1096 op->mode = OP_REG;1097 }1098 else if (x == 8)1099 {1100 op->reg = 2;1101 op->am = 3;1102 op->ol = 0;1103 op->mode = OP_REG;1104 }1105 1256 } 1106 1257 /* Redundant (yet) check. */ 1107 1258 else if (op->exp.X_op == O_register) … … msp430_srcoperand (struct msp430_operand_s * op, 1128 1279 { 1129 1280 int x = op->exp.X_add_number; 1130 1281 1131 if (x > 65535 || x < -32768)1282 if (x >= imm_max || x < imm_min) 1132 1283 { 1133 1284 as_bad (_("value out of range: %d"), x); 1134 1285 return 1; … … msp430_srcoperand (struct msp430_operand_s * op, 1263 1414 { 1264 1415 int x = op->exp.X_add_number; 1265 1416 1266 if (x > 65535 || x < -32768)1417 if (x > imm_max || x < imm_min) 1267 1418 { 1268 1419 as_bad (_("value out of range: %d"), x); 1269 1420 return 1; … … msp430_srcoperand (struct msp430_operand_s * op, 1339 1490 1340 1491 1341 1492 static int 1342 msp430_dstoperand (struct msp430_operand_s * op, char * l, int bin)1493 msp430_dstoperand (struct msp430_operand_s * op, char * l, int imm_min, int imm_max) 1343 1494 { 1344 1495 int dummy; 1345 int ret = msp430_srcoperand (op, l, bin, & dummy);1496 int ret = msp430_srcoperand (op, l, & dummy, imm_min, imm_max); 1346 1497 1347 1498 if (ret) 1348 1499 return ret; … … msp430_dstoperand (struct msp430_operand_s * op, char * l, int bin) 1374 1525 return 0; 1375 1526 } 1376 1527 1528 static void 1529 msp430_repeat_insn (int dummy ATTRIBUTE_UNUSED) 1530 { 1531 char operand[MAX_OP_LEN]; 1532 struct msp430_operand_s op; 1533 int imm_op = 0; 1534 char *line = input_line_pointer; 1535 1536 if (msp430_core(msp430_mcu) < CORE_430X) 1537 { 1538 as_bad (_("Repeatable instructions not allowed with %s mcu"), msp430_mcu->name); 1539 return; 1540 } 1541 1542 if (msp430x_repeats) 1543 as_warn (_("two consecutive .rpt pseudo-ops. Previous .rpt discarded")); 1544 1545 if (!*line || *line == '\n') 1546 { 1547 as_bad (_("rpt pseudo-op requires 1 operand")); 1548 return; 1549 } 1550 1551 memset (&op, 0, sizeof (op)); 1552 1553 input_line_pointer = extract_operand (line, operand, sizeof(operand)); 1554 1555 if (msp430_srcoperand(&op, operand, &imm_op, 1, 15) != 0) 1556 return; 1557 1558 if ( !(op.mode == OP_REG && op.am == 0) // Rn 1559 && !(op.mode == OP_EXP && op.am == 3) // #N 1560 ) 1561 { 1562 as_bad (_("rpt pseudo-op requires immediate or register operand")); 1563 return; 1564 } 1565 1566 if (op.am == 0) // rpt Rn 1567 msp430x_repeats = (((1 << 7) | op.reg) << 1) | 1; // last bit as .rpt flag 1568 else // rpt #N 1569 msp430x_repeats = ((op.exp.X_add_number - 1) << 1) | 1; // last bit as .rpt flag 1570 } 1377 1571 1378 1572 /* Parse instruction operands. 1379 1573 Return binary opcode. */ 1380 1574 1381 1575 static unsigned int 1382 msp430_operands (struct msp430_opcode_s * opcode, char * line)1576 msp430_operands (struct msp430_opcode_s const * opcode, char * line) 1383 1577 { 1384 1578 int bin = opcode->bin_opcode; /* Opcode mask. */ 1385 1579 int __is = 0; 1386 1580 char l1[MAX_OP_LEN], l2[MAX_OP_LEN]; 1387 char *frag ;1388 int where ;1581 char *frag = 0; 1582 int where = 0; 1389 1583 struct msp430_operand_s op1, op2; 1390 1584 int res = 0; 1391 1585 static short ZEROS = 0; 1392 int byte_op, imm_op; 1393 1586 int imm_op; 1587 opwidth_t op_width = DEFAULT_OP; 1588 1394 1589 /* Opcode is the one from opcodes table 1395 1590 line contains something like 1396 1591 [.w] @r2+, 5(R1) 1397 1592 or 1398 .b @r2+, 5(R1). */ 1593 .b @r2+, 5(R1) 1594 or 1595 .a @r2+, 5(R1) */ 1399 1596 1400 1597 /* Check if byte or word operation. */ 1598 1401 1599 if (*line == '.' && TOLOWER (*(line + 1)) == 'b') 1402 1600 { 1403 bin |= BYTE_OPERATION; 1404 byte_op = 1; 1601 op_width = BYTE_OP; 1602 } 1603 else if (*line == '.' && TOLOWER (*(line + 1)) == 'w') 1604 { 1605 op_width = WORD_OP; 1606 } 1607 else if (*line == '.' && TOLOWER (*(line + 1)) == 'a') 1608 { 1609 op_width = ADDR_OP; 1405 1610 } 1406 else1407 byte_op = 0;1408 1611 1409 /* skip .[bwBW]. */ 1612 if ((op_width == WORD_OP && !(opcode_modifier(opcode) & MOD_W)) 1613 || (op_width == BYTE_OP && !(opcode_modifier(opcode) & MOD_B)) 1614 || (op_width == ADDR_OP && !(opcode_modifier(opcode) & MOD_A)) 1615 ) 1616 { 1617 static char* const modifier[] = { "", ".w", ".b", ".a" }; 1618 as_bad (_("%s not allowed with %s instruction"), 1619 modifier[op_width], opcode->name); 1620 return 0; 1621 } 1622 1623 if ( opcode_format(opcode) == FMT_X_DOUBLE_OPERAND 1624 || opcode_format(opcode) == FMT_X_SINGLE_OPERAND 1625 || opcode_format(opcode) == FMT_X_EMULATED 1626 ) 1627 { 1628 switch(op_width) 1629 { 1630 case DEFAULT_OP: 1631 case WORD_OP: 1632 bin |= NON_ADDR_OPERATION; 1633 break; 1634 case BYTE_OP: 1635 bin |= NON_ADDR_OPERATION; 1636 bin |= BYTE_OPERATION_X; 1637 break; 1638 case ADDR_OP: 1639 bin |= BYTE_OPERATION_X; 1640 break; 1641 } 1642 } 1643 else 1644 { 1645 if(msp430x_repeats) 1646 { 1647 as_bad (_("%s instruction is not repeatable"), opcode->name); 1648 return 0; 1649 } 1650 1651 if ( opcode_format(opcode) < FMT_X && op_width == BYTE_OP ) // 430 instructions 1652 { 1653 bin |= BYTE_OPERATION; 1654 } 1655 } 1656 /* skip .[abwABW]. */ 1410 1657 while (! ISSPACE (*line) && *line) 1411 1658 line++; 1412 1659 … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1424 1671 1425 1672 imm_op = 0; 1426 1673 1427 switch (opcode ->fmt)1674 switch (opcode_format(opcode)) 1428 1675 { 1429 case 0: /* Emulated. */1430 switch (opcode ->insn_opnumb)1676 case FMT_EMULATED: /* Emulated. */ 1677 switch (opcode_variant(opcode)) 1431 1678 { 1432 case 0:1433 /* Set/clear bits instructions.*/1679 case V_NOOP: 1680 /* Set/clear SR bits instructions, ret, nop */ 1434 1681 __is = 2; 1435 1682 frag = frag_more (__is); 1436 1683 bfd_putl16 ((bfd_vma) bin, frag); 1437 1684 dwarf2_emit_insn (__is); 1438 1685 break; 1439 case 1:1686 case V_NONE: 1440 1687 /* Something which works with destination operand. */ 1441 1688 line = extract_operand (line, l1, sizeof (l1)); 1442 res = msp430_dstoperand (&op1, l1, opcode->bin_opcode);1689 res = msp430_dstoperand (&op1, l1, -(1<<15), (1<<16) ); 1443 1690 if (res) 1444 1691 break; 1445 1692 … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1464 1711 } 1465 1712 break; 1466 1713 1467 case 2:1714 case V_SHIFT: 1468 1715 { 1469 1716 /* Shift instruction. */ 1470 1717 line = extract_operand (line, l1, sizeof (l1)); 1471 1718 strncpy (l2, l1, sizeof (l2)); 1472 1719 l2[sizeof (l2) - 1] = '\0'; 1473 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op); 1474 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode); 1720 res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<15), (1<<16)); 1721 msp430_substitute_CG(&op1, 0); 1722 res += msp430_dstoperand (&op2, l2, -(1<<15), (1<<16)); 1475 1723 1476 1724 if (res) 1477 1725 break; /* An error occurred. All warnings were done before. */ … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1499 1747 1500 1748 if (op2.mode == OP_EXP) 1501 1749 { 1502 imm_op = 0; 1750 /* 1751 x(Rn). x can be odd in non-byte operations 1752 except x(R2) = x(0) = &TONI and x(PC) = TONI 1753 */ 1754 imm_op = (op2.mode == 1 && op2.reg != 2 && op2.reg != 0); 1755 1503 1756 bfd_putl16 ((bfd_vma) ZEROS, frag + 2 + ((__is == 3) ? 2 : 0)); 1504 1757 1505 1758 if (op2.reg) /* Not PC relative. */ … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1511 1764 } 1512 1765 break; 1513 1766 } 1514 case 3:1767 case V_BR: 1515 1768 /* Branch instruction => mov dst, r0. */ 1516 1769 line = extract_operand (line, l1, sizeof (l1)); 1517 1770 1518 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op); 1771 res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<15), (1<<16)); 1772 msp430_substitute_CG(&op1, 0); 1519 1773 if (res) 1520 1774 break; 1521 1775 1522 byte_op = 0; 1523 imm_op = 0; 1776 if (op1.mode == 1 && (op1.reg == 2 || op1.reg == 0)) 1777 /* 1778 x(Rn). x can be odd in non-byte operations 1779 except x(R2) = x(0) = &EDE and x(PC) = EDE 1780 */ 1781 imm_op = 0; 1524 1782 1525 1783 bin |= ((op1.reg << 8) | (op1.am << 4)); 1526 1784 __is = 1 + op1.ol; … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1545 1803 } 1546 1804 break; 1547 1805 1548 case 1:/* Format 1, double operand. */1806 case FMT_DOUBLE_OPERAND: /* Format 1, double operand. */ 1549 1807 line = extract_operand (line, l1, sizeof (l1)); 1550 1808 line = extract_operand (line, l2, sizeof (l2)); 1551 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op); 1552 res += msp430_dstoperand (&op2, l2, opcode->bin_opcode); 1809 res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<15), (1<<16)); 1810 msp430_substitute_CG(&op1, 0); 1811 res += msp430_dstoperand (&op2, l2, -(1<<15), (1<<16)); 1553 1812 1554 1813 if (res) 1555 1814 break; /* Error occurred. All warnings were done before. */ … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1577 1836 1578 1837 if (op2.mode == OP_EXP) 1579 1838 { 1580 imm_op = 0; 1839 /* 1840 x(Rn). x can be odd in non-byte operations 1841 except x(R2) = x(0) = &TONI and x(PC) = TONI 1842 */ 1843 imm_op = (op2.mode == 1 && op2.reg != 2 && op2.reg != 0); 1844 1581 1845 bfd_putl16 ((bfd_vma) ZEROS, frag + 2 + ((__is == 3) ? 2 : 0)); 1582 1846 1583 1847 if (op2.reg) /* Not PC relative. */ … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1589 1853 } 1590 1854 break; 1591 1855 1592 case 2: /* Single-operand mostly instr. */1593 if (opcode ->insn_opnumb == 0)1856 case FMT_SINGLE_OPERAND: /* Single-operand mostly instr. */ 1857 if (opcode_variant(opcode) == V_RETI) 1594 1858 { 1595 1859 /* reti instruction. */ 1596 1860 frag = frag_more (2); … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1600 1864 } 1601 1865 1602 1866 line = extract_operand (line, l1, sizeof (l1)); 1603 res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op);1867 res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<15), (1<<16)); 1604 1868 if (res) 1605 1869 break; /* Error in operand. */ 1870 msp430_substitute_CG(&op1, (msp430_mcu->isa & CPU4_BUG) && (opcode->bin_opcode == 0x1200)); 1606 1871 1607 1872 bin |= op1.reg | (op1.am << 4); 1608 1873 __is = 1 + op1.ol; … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1624 1889 } 1625 1890 break; 1626 1891 1627 case 3: /* Conditional jumps instructions. */1892 case FMT_JUMP: /* Conditional jumps instructions. */ 1628 1893 line = extract_operand (line, l1, sizeof (l1)); 1629 1894 /* l1 is a label. */ 1630 1895 if (l1[0]) … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1694 1959 else if (*l1 == '$') 1695 1960 { 1696 1961 as_bad (_("instruction requires label sans '$'")); 1962 break; 1697 1963 } 1698 1964 else 1699 1965 { 1700 1966 as_bad (_ 1701 1967 ("instruction requires label or value in range -511:512")); 1968 break; 1702 1969 } 1703 1970 dwarf2_emit_insn (2 * __is); 1704 1971 break; … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1710 1977 } 1711 1978 break; 1712 1979 1713 case 4: /* Extended jumps. */1980 case FMT_EMULATED_POLYMORPH_JUMP: /* Extended jumps. */ 1714 1981 if (!msp430_enable_polys) 1715 1982 { 1716 1983 as_bad (_("polymorphs are not enabled. Use -mP option to enable.")); … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1731 1998 if (exp.X_op == O_symbol) 1732 1999 { 1733 2000 /* Relaxation required. */ 1734 struct rcodes_s rc = msp430_rcodes[opcode ->insn_opnumb];2001 struct rcodes_s rc = msp430_rcodes[opcode_variant(opcode)]; 1735 2002 1736 2003 /* The parameter to dwarf2_emit_insn is actually the offset to the start 1737 2004 of the insn from the fix piece of instruction that was emitted. … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1752 2019 as_bad (_("instruction requires label")); 1753 2020 break; 1754 2021 1755 case 5: /* Emulated extended branches. */2022 case FMT_EMULATED_LONG_POLYMORPH_JUMP: /* Emulated extended branches. */ 1756 2023 if (!msp430_enable_polys) 1757 2024 { 1758 2025 as_bad (_("polymorphs are not enabled. Use -mP option to enable.")); … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1772 2039 if (exp.X_op == O_symbol) 1773 2040 { 1774 2041 /* Relaxation required. */ 1775 struct hcodes_s hc = msp430_hcodes[opcode ->insn_opnumb];2042 struct hcodes_s hc = msp430_hcodes[opcode_variant(opcode)]; 1776 2043 1777 2044 frag = frag_more (8); 1778 2045 dwarf2_emit_insn (0); … … msp430_operands (struct msp430_opcode_s * opcode, char * line) 1791 2058 as_bad (_("instruction requires label")); 1792 2059 break; 1793 2060 2061 case FMT_X_DOUBLE_OPERAND: /* Extended Format 1 ( double operand). */ 2062 line = extract_operand (line, l1, sizeof (l1)); 2063 line = extract_operand (line, l2, sizeof (l2)); 2064 res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<19), (1<<20)); 2065 msp430_substitute_CG(&op1, 0); 2066 res += msp430_dstoperand (&op2, l2, -(1<<19), (1<<20)); 2067 2068 if (res) 2069 break; /* Error occurred. All warnings were done before. */ 2070 2071 if (msp430x_repeats) 2072 { 2073 if (op1.mode != OP_REG || op2.mode != OP_REG) 2074 { 2075 as_bad(_("Repeated instruction must have register mode operands")); 2076 break; 2077 } 2078 bin |= msp430x_repeats >> 1; 2079 msp430x_repeats = 0; 2080 } 2081 2082 bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7)) << 16; 2083 2084 __is = 2 + op1.ol + op2.ol; /* insn size in words, opcode is 2 words wide. */ 2085 frag = frag_more (2 * __is); 2086 where = frag - frag_now->fr_literal; 2087 bfd_putl32 ((bfd_vma) bin, frag); 2088 dwarf2_emit_insn (2 * __is); 2089 2090 if (op1.mode == OP_EXP) 2091 { 2092 bfd_putl16 ((bfd_vma) ZEROS, frag + 4); 2093 2094 if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ 2095 fix_new_exp (frag_now, where, 2, 2096 &(op1.exp), FALSE, CHECK_RELOC_MSP430X_SRC); 2097 else 2098 fix_new_exp (frag_now, where , 2, 2099 &(op1.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_SRC); 2100 } 2101 2102 if (op2.mode == OP_EXP) 2103 { 2104 /* 2105 x(Rn). x can be odd in non-byte operations 2106 except x(R2) = x(0) = &TONI and x(PC) = TONI 2107 */ 2108 imm_op = (op2.mode == 1 && op2.reg != 2 && op2.reg != 0); 2109 bfd_putl16 ((bfd_vma) ZEROS, frag + 4 + ((__is == 4) ? 2 : 0)); 2110 2111 if (op1.mode == OP_EXP) 2112 { 2113 if (op2.reg) /* Not PC relative. */ 2114 fix_new_exp (frag_now, where, 2, 2115 &(op2.exp), FALSE, CHECK_RELOC_MSP430X_DST_2ND); 2116 else 2117 fix_new_exp (frag_now, where, 2, 2118 &(op2.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_DST_2ND); 2119 } 2120 else 2121 { 2122 if (op2.reg) /* Not PC relative. */ 2123 fix_new_exp (frag_now, where, 2, 2124 &(op2.exp), FALSE, CHECK_RELOC_MSP430X_DST); 2125 else 2126 fix_new_exp (frag_now, where, 2, 2127 &(op2.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_DST); 2128 } 2129 } 2130 break; 2131 2132 case FMT_X_SINGLE_OPERAND: /* Extended format 2 (single-operand). */ 2133 line = extract_operand (line, l1, sizeof (l1)); 2134 res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<19), (1<<20)); 2135 msp430_substitute_CG(&op1, 0); 2136 if (res) 2137 break; /* Error in operand. */ 2138 2139 if (opcode_variant(opcode) != V_PUSHX && op1.mode == OP_EXP && op1.am == 3) // #N 2140 { 2141 as_bad (_("bad operand [%s]"), l1); 2142 break; 2143 } 2144 2145 if (msp430x_repeats) 2146 { 2147 if (op1.mode != OP_REG) 2148 { 2149 as_bad(_("Repeated instruction must have register mode operand")); 2150 break; 2151 } 2152 bin |= msp430x_repeats >> 1; 2153 msp430x_repeats = 0; 2154 } 2155 2156 if(opcode_variant(opcode) == V_SWPSXT && op_width == ADDR_OP) 2157 { // sxtx.a | swpbx.a opcode 2158 bin ^= BYTE_OPERATION_X; 2159 } 2160 2161 bin |= (op1.reg | (op1.am << 4)) << 16; 2162 __is = 2 + op1.ol; /* insn size in words, opcode is 2 words wide. */ 2163 frag = frag_more (2 * __is); 2164 where = frag - frag_now->fr_literal; 2165 bfd_putl32 ((bfd_vma) bin, frag); 2166 dwarf2_emit_insn (2 * __is); 2167 2168 if (op1.mode == OP_EXP) 2169 { 2170 bfd_putl16 ((bfd_vma) ZEROS, frag + 4); 2171 2172 if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ 2173 fix_new_exp (frag_now, where, 2, 2174 &(op1.exp), FALSE, CHECK_RELOC_MSP430X_DST); 2175 else 2176 fix_new_exp (frag_now, where, 2, 2177 &(op1.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_DST); 2178 } 2179 break; 2180 2181 case FMT_X_EXCEPTION: 2182 /* calla, pushm, popm, rrcm, rrum, rram, rlam */ 2183 bin = opcode->bin_opcode; // remove WB/AL bits 2184 line = extract_operand (line, l1, sizeof (l1)); 2185 switch(opcode_variant(opcode)) 2186 { 2187 case V_CALLA: // calla 2188 res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<19), (1<<20)); 2189 if (res) 2190 break; /* Error in operand. */ 2191 __is = 1 + op1.ol; 2192 frag = frag_more(__is * 2); 2193 2194 if (op1.mode == OP_REG) 2195 { 2196 bin |= op1.reg; 2197 switch (op1.am) 2198 { 2199 case 0: // Rdst 2200 bin |= 0x0040; 2201 break; 2202 case 2: // @Rdst 2203 bin |= 0x0060; 2204 break; 2205 case 3: // @Rdst+ 2206 bin |= 0x0070; 2207 break; 2208 } 2209 bin |= op1.reg; 2210 bfd_putl16 ((bfd_vma) bin, frag); 2211 dwarf2_emit_insn (__is * 2); 2212 } 2213 else if (op1.mode == OP_EXP) 2214 { 2215 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 2216 where = frag - frag_now->fr_literal; 2217 switch (op1.am) 2218 { 2219 case 1: 2220 switch(op1.reg) 2221 { 2222 case 0: // x(PC) = EDE 2223 bin |= 0x0090; 2224 bfd_putl16 ((bfd_vma) bin, frag); 2225 fix_new_exp (frag_now, where, 2, 2226 &(op1.exp), TRUE, BFD_RELOC_MSP430X_PCREL_D); 2227 break; 2228 case 2: // &abs20 2229 bin |= 0x0080; 2230 bfd_putl16 ((bfd_vma) bin, frag); 2231 fix_new_exp (frag_now, where, 2, 2232 &(op1.exp), FALSE, BFD_RELOC_MSP430X_D); 2233 break; 2234 default: //z16(Rdst) 2235 bin |= 0x0050 | op1.reg; 2236 bfd_putl16 ((bfd_vma) bin, frag); 2237 fix_new_exp (frag_now, where, 2, 2238 &(op1.exp), FALSE, BFD_RELOC_MSP430X_INDXD); 2239 break; 2240 } 2241 break; 2242 case 3: // calla #imm 2243 bin |= 0x00b0; 2244 bfd_putl16 ((bfd_vma) bin, frag); 2245 fix_new_exp (frag_now, where, 2, 2246 &(op1.exp), FALSE, BFD_RELOC_MSP430X_D); 2247 break; 2248 } 2249 dwarf2_emit_insn (__is * 2); 2250 } 2251 break; 2252 case V_ROTM: // rxxm 2253 line = extract_operand(line, l2, sizeof(l2)); 2254 res = msp430_srcoperand (&op1, l1, &imm_op, 1, 5); 2255 res += msp430_dstoperand (&op2, l2, -(1<<19), (1<<20)); 2256 if(res) 2257 break; /* An error occurred. All warnings were done before. */ 2258 2259 if(op_width != ADDR_OP) 2260 bin |= (1 << 4); 2261 2262 if(op1.mode != OP_EXP || op1.am != 3) // not #imm 2263 { 2264 as_bad (_("bad operand [%s]"), l1); 2265 break; 2266 } 2267 2268 bin |= ((op1.exp.X_add_number - 1) & 0x0003) << 10; 2269 2270 if(op2.mode != OP_REG) 2271 { 2272 as_bad (_("bad operand [%s]"), l2); 2273 break; 2274 } 2275 bin |= op2.reg; 2276 2277 frag = frag_more (2); 2278 bfd_putl16 ((bfd_vma) bin, frag); 2279 dwarf2_emit_insn (2); 2280 break; 2281 case V_PUSHM: 2282 case V_POPM: 2283 line = extract_operand(line, l2, sizeof(l2)); 2284 res = msp430_srcoperand (&op1, l1, &imm_op, 1, 17); 2285 res += msp430_dstoperand (&op2, l2, -(1<<19), (1<<20)); 2286 if(res) 2287 break; /* An error occurred. All warnings were done before. */ 2288 2289 2290 if(imm_op == 0) 2291 { 2292 as_bad (_("bad operand [%s]"), l1); 2293 break; 2294 } 2295 2296 if(op_width != ADDR_OP) 2297 { 2298 bin |= (1 << 8); 2299 } 2300 bin |= ((op1.exp.X_add_number - 1) & 0x000F) << 4; 2301 2302 if(op2.mode != OP_REG) 2303 { 2304 as_bad (_("bad operand [%s]"), l2); 2305 break; 2306 } 2307 if(opcode_variant(opcode) == V_POPM) 2308 { 2309 /* popm */ 2310 bin |= (op2.reg - op1.exp.X_add_number + 1) & 0x000F; 2311 } 2312 else 2313 { 2314 /* pushm */ 2315 bin |= op2.reg; 2316 } 2317 2318 frag = frag_more (2); 2319 bfd_putl16 ((bfd_vma) bin, frag); 2320 dwarf2_emit_insn (2); 2321 break; 2322 } 2323 break; 2324 case FMT_X_ADDRESS: 2325 /* mova, adda, suba, cmpa */ 2326 line = extract_operand (line, l1, sizeof (l1)); 2327 line = extract_operand (line, l2, sizeof (l2)); 2328 res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<19), (1<<20)); 2329 res += msp430_dstoperand (&op2, l2, -(1<<19), (1<<20)); 2330 if (res) 2331 break; /* Error in operand. */ 2332 2333 __is = 1 + op1.ol + op2.ol; 2334 frag = frag_more(__is * 2); 2335 where = frag - frag_now->fr_literal; 2336 bin = opcode->bin_opcode; // remove WB/AL bits 2337 if( opcode_variant(opcode) == V_MOVA) 2338 { 2339 if (op1.mode == OP_REG && op1.am == 0) 2340 { // Rsrc 2341 if(op2.mode == OP_REG && op2.am == 0) 2342 { 2343 // mova Rsrc, Rdst 2344 bin |= 0x00c0 | op1.reg << 8 | op2.reg; 2345 bfd_putl16 ((bfd_vma) bin, frag); 2346 dwarf2_emit_insn (__is * 2); 2347 } 2348 else if(op2.mode == OP_EXP && op2.am == 1 && op2.reg == 2) 2349 { 2350 // mova Rsrc, &abs20 2351 bin |= 0x0060 | op1.reg << 8; 2352 bfd_putl16 ((bfd_vma) bin, frag); 2353 dwarf2_emit_insn (__is * 2); 2354 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 2355 fix_new_exp (frag_now, where, 2, 2356 &(op2.exp), FALSE, BFD_RELOC_MSP430X_D); 2357 } 2358 else if(op2.mode == OP_EXP && op2.am == 1 && op2.reg == 0) 2359 { 2360 bin |= 0x0070 | op1.reg << 8; 2361 bfd_putl16 ((bfd_vma) bin, frag); 2362 dwarf2_emit_insn (__is * 2); 2363 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 2364 fix_new_exp (frag_now, where, 2, 2365 &(op2.exp), TRUE, BFD_RELOC_MSP430X_PCREL_D); 2366 } 2367 else if(op2.mode == OP_EXP && op2.am == 1) 2368 { 2369 // mova Rsrc, z16(Rdst) 2370 bin |= 0x0070 | op1.reg << 8 | op2.reg; 2371 bfd_putl16 ((bfd_vma) bin, frag); 2372 dwarf2_emit_insn (__is * 2); 2373 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 2374 if(op2.reg == 0) 2375 // mova Rsrc, TONI == mova Rsrc, z16(PC) 2376 fix_new_exp (frag_now, where, 2, 2377 &(op2.exp), TRUE, BFD_RELOC_MSP430X_PCREL_INDXD); 2378 else 2379 fix_new_exp (frag_now, where, 2, 2380 &(op2.exp), FALSE, BFD_RELOC_MSP430X_INDXD); 2381 } 2382 else 2383 as_bad (_("destination operand address mode not allowed with mova instruction")); 2384 2385 } 2386 else if (op2.mode == OP_REG && op2.am == 0) 2387 { // Rdst 2388 if(op1.mode == OP_REG && op1.am == 2) 2389 { 2390 // mova @Rsrc, Rdst 2391 bin |= 0x0000 | op1.reg << 8 | op2.reg; 2392 bfd_putl16 ((bfd_vma) bin, frag); 2393 dwarf2_emit_insn (__is * 2); 2394 } 2395 else if (op1.mode == OP_REG && op1.am == 3) 2396 { 2397 // mova @Rsrc+, Rdst 2398 bin |= 0x0010 | op1.reg << 8 | op2.reg; 2399 bfd_putl16 ((bfd_vma) bin, frag); 2400 dwarf2_emit_insn (__is * 2); 2401 } 2402 else if (op1.mode == OP_EXP && op1.am == 1 && op1.reg == 2) 2403 { 2404 if (op1.reg == 2) 2405 { 2406 // mova &abs20, Rdst 2407 bin |= 0x0020 | op2.reg; 2408 bfd_putl16 ((bfd_vma) bin, frag); 2409 dwarf2_emit_insn (__is * 2); 2410 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 2411 fix_new_exp (frag_now, where, 2, 2412 &(op1.exp), FALSE, BFD_RELOC_MSP430X_S); 2413 } 2414 else 2415 { 2416 // mova z16(Rsrc), Rdst 2417 bin |= 0x0030 | op1.reg << 8 | op2.reg; 2418 bfd_putl16 ((bfd_vma) bin, frag); 2419 dwarf2_emit_insn (__is * 2); 2420 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 2421 if (op1.reg == 0) 2422 // mova TONI, Rdst 2423 fix_new_exp (frag_now, where, 2, 2424 &(op1.exp), FALSE, BFD_RELOC_MSP430X_PCREL_INDXD); 2425 else 2426 fix_new_exp (frag_now, where, 2, 2427 &(op1.exp), FALSE, BFD_RELOC_MSP430X_INDXD); 2428 } 2429 } 2430 else if (op1.mode == OP_EXP && op1.am == 3) 2431 { 2432 // mova #imm20, Rdst 2433 bin |= 0x0080 | op2.reg; 2434 bfd_putl16 ((bfd_vma) bin, frag); 2435 dwarf2_emit_insn (__is * 2); 2436 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 2437 if (op2.reg == 0) 2438 fix_new_exp (frag_now, where, 2, 2439 &(op1.exp), FALSE, BFD_RELOC_MSP430X_S); 2440 else 2441 fix_new_exp (frag_now, where, 2, 2442 &(op1.exp), FALSE, BFD_RELOC_MSP430X_S_BYTE); 2443 } 2444 else 2445 as_bad (_("source operand address mode not allowed with mova instruction")); 2446 } 2447 break; 2448 } 2449 else 2450 /* adda, suba, cmpa */ 2451 { 2452 if(op2.mode == OP_REG && op2.am == 0) 2453 { 2454 if (op1.mode == OP_REG && op1.am == 0) 2455 { // Rsrc, Rdst 2456 bin |= 0x0040 | op1.reg << 8 | op2.reg; 2457 bfd_putl16 ((bfd_vma) bin, frag); 2458 dwarf2_emit_insn (__is * 2); 2459 } 2460 else if (op1.mode == OP_EXP && op1.am == 3) 2461 { 2462 // #imm20, Rdst 2463 bin |= 0x0080 | op2.reg; 2464 bfd_putl16 ((bfd_vma) bin, frag); 2465 dwarf2_emit_insn (__is * 2); 2466 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 2467 if (op2.reg == 0) 2468 fix_new_exp (frag_now, where, 2, 2469 &(op1.exp), FALSE, BFD_RELOC_MSP430X_S); 2470 else 2471 fix_new_exp (frag_now, where, 2, 2472 &(op1.exp), FALSE, BFD_RELOC_MSP430X_S_BYTE); 2473 } 2474 else 2475 as_bad (_("source operand address mode not allowed with %s instruction"), opcode->name); 2476 } 2477 else 2478 as_bad (_("destination operand address mode not allowed with %s instruction"), opcode->name); 2479 break; 2480 } 2481 break; 2482 2483 case FMT_X_EMULATED: /* Extended emulated. */ 2484 switch (opcode_variant(opcode)) 2485 { 2486 case V_NONE: 2487 /* single operand instruction emulated with Extended type 1 (double operand) instructions. */ 2488 line = extract_operand (line, l1, sizeof (l1)); 2489 res = msp430_dstoperand (&op1, l1, -(1<<19), (1<<20) ); 2490 if (res) 2491 break; 2492 2493 if (msp430x_repeats) 2494 { 2495 if ((bin >> 20) && 0x3 == 1) 2496 { 2497 as_bad (_("%s instruction is not repeatable"), opcode->name); 2498 break; 2499 } 2500 if (op1.mode != OP_REG) 2501 { 2502 as_bad(_("Repeated instruction must have register mode operand")); 2503 break; 2504 } 2505 bin |= msp430x_repeats >> 1; 2506 msp430x_repeats = 0; 2507 } 2508 2509 bin |= (op1.reg | (op1.am << 7)) << 16; 2510 __is = 2 + op1.ol; 2511 frag = frag_more (2 * __is); 2512 where = frag - frag_now->fr_literal; 2513 bfd_putl32 ((bfd_vma) bin, frag); 2514 dwarf2_emit_insn (2 * __is); 2515 2516 if (op1.mode == OP_EXP) 2517 { 2518 /* 2519 x(Rn). x can be odd in non-byte operations 2520 except x(R2) = x(0) = &TONI and x(PC) = TONI 2521 */ 2522 imm_op = (op2.mode == 1 && op2.reg != 2 && op2.reg != 0); 2523 2524 bfd_putl16 ((bfd_vma) ZEROS, frag + 4); 2525 if (op1.reg || (op1.reg == 0 && op1.am == 3)) 2526 fix_new_exp (frag_now, where, 2, 2527 &(op1.exp), FALSE, CHECK_RELOC_MSP430X_DST); 2528 else 2529 fix_new_exp (frag_now, where, 2, 2530 &(op1.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_DST); 2531 } 2532 break; 2533 case V_X_SHIFT: 2534 { 2535 /* Shift instruction. */ 2536 line = extract_operand (line, l1, sizeof (l1)); 2537 strncpy (l2, l1, sizeof (l2)); 2538 l2[sizeof (l2) - 1] = '\0'; 2539 res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<19), (1<<20)); 2540 msp430_substitute_CG(&op1, 0); 2541 res += msp430_dstoperand (&op2, l2, -(1<<19), (1<<20)); 2542 2543 if (res) 2544 break; /* An error occurred. All warnings were done before. */ 2545 2546 if (msp430x_repeats) 2547 { 2548 if (op2.mode != OP_REG) 2549 { 2550 as_bad(_("Repeated instruction must have register mode operands")); 2551 break; 2552 } 2553 bin |= msp430x_repeats >> 1; 2554 msp430x_repeats = 0; 2555 } 2556 2557 bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7)) << 16; 2558 2559 __is = 2 + op1.ol + op2.ol; /* insn size in words. */ 2560 frag = frag_more (2 * __is); 2561 where = frag - frag_now->fr_literal; 2562 bfd_putl32 ((bfd_vma) bin, frag); 2563 dwarf2_emit_insn (2 * __is); 2564 2565 if (op1.mode == OP_EXP) 2566 { 2567 bfd_putl16 ((bfd_vma) ZEROS, frag + 4); 2568 2569 if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ 2570 fix_new_exp (frag_now, where, 2, 2571 &(op1.exp), FALSE, CHECK_RELOC_MSP430X_SRC); 2572 else 2573 fix_new_exp (frag_now, where, 2, 2574 &(op1.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_SRC); 2575 } 2576 2577 if (op2.mode == OP_EXP) 2578 { 2579 /* 2580 x(Rn). x can be odd in non-byte operations 2581 except x(R2) = x(0) = &TONI and x(PC) = TONI 2582 */ 2583 imm_op = (op2.mode == 1 && op2.reg != 2 && op2.reg != 0); 2584 2585 bfd_putl16 ((bfd_vma) ZEROS, frag + 4 + ((__is == 4) ? 2 : 0)); 2586 if (op1.mode == OP_EXP) 2587 { 2588 2589 if (op2.reg) /* Not PC relative. */ 2590 fix_new_exp (frag_now, where, 2, 2591 &(op2.exp), FALSE, CHECK_RELOC_MSP430X_DST_2ND); 2592 else 2593 fix_new_exp (frag_now, where, 2, 2594 &(op2.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_DST_2ND); 2595 } 2596 else 2597 { 2598 2599 if (op2.reg) /* Not PC relative. */ 2600 fix_new_exp (frag_now, where, 2, 2601 &(op2.exp), FALSE, CHECK_RELOC_MSP430X_DST); 2602 else 2603 fix_new_exp (frag_now, where, 2, 2604 &(op2.exp), TRUE, CHECK_RELOC_MSP430X_PCREL_DST); 2605 } 2606 } 2607 } 2608 break; 2609 case V_RETA: 2610 /* reta */ 2611 if (msp430x_repeats) 2612 { 2613 as_bad (_("%s instruction is not repeatable"), opcode->name); 2614 break; 2615 } 2616 bin = opcode->bin_opcode; // remove WB/AL bits 2617 frag = frag_more (2); 2618 bfd_putl16 ((bfd_vma) bin, frag); 2619 dwarf2_emit_insn (2); 2620 break; 2621 case V_EMU_ADDR: // incda, decda, tsta 2622 if (msp430x_repeats) 2623 { 2624 as_bad (_("%s instruction is not repeatable"), opcode->name); 2625 break; 2626 } 2627 bin = opcode->bin_opcode; // remove WB/AL bits 2628 line = extract_operand (line, l1, sizeof (l1)); 2629 res = msp430_dstoperand (&op1, l1, -(1<<19), (1<<20) ); 2630 if (res) 2631 break; 2632 2633 if(op1.mode == OP_REG && op1.am == 0) 2634 { 2635 frag = frag_more(2); 2636 bin |= op1.reg; 2637 bfd_putl16 ((bfd_vma) bin, frag); 2638 dwarf2_emit_insn (2); 2639 } 2640 else 2641 as_bad (_("destination operand address mode not allowed with %s instruction"), opcode->name); 2642 break; 2643 case V_BRA: // bra, emulated with Address type instruction 2644 if (msp430x_repeats) 2645 { 2646 as_bad (_("%s instruction is not repeatable"), opcode->name); 2647 break; 2648 } 2649 2650 bin = opcode->bin_opcode; // remove WB/AL bits 2651 line = extract_operand (line, l1, sizeof (l1)); 2652 res = msp430_srcoperand (&op1, l1, &imm_op, -(1<<19), (1<<20)); 2653 if (res) 2654 break; /* Error in operand. */ 2655 2656 __is = 1 + op1.ol; 2657 frag = frag_more(__is * 2); 2658 where = frag - frag_now->fr_literal; 2659 if (op1.mode == OP_REG && op1.am == 0) 2660 { 2661 // mova Rsrc, PC 2662 bin |= 0x00C0 | op1.reg << 8; 2663 bfd_putl16 ((bfd_vma) bin, frag); 2664 dwarf2_emit_insn (__is * 2); 2665 } 2666 else if(op1.mode == OP_REG && op1.am == 2) 2667 { 2668 // mova @Rsrc, PC 2669 bin |= 0x0000 | op1.reg << 8; 2670 bfd_putl16 ((bfd_vma) bin, frag); 2671 dwarf2_emit_insn (__is * 2); 2672 } 2673 else if (op1.mode == OP_REG && op1.am == 3) 2674 { 2675 // mova @Rsrc+, PC 2676 bin |= 0x0010 | op1.reg << 8; 2677 bfd_putl16 ((bfd_vma) bin, frag); 2678 dwarf2_emit_insn (__is * 2); 2679 } 2680 else if (op1.mode == OP_EXP && op1.am == 1) 2681 { 2682 if (op1.reg == 2) 2683 { 2684 // mova &abs20, PC 2685 bin |= 0x0020; 2686 bfd_putl16 ((bfd_vma) bin, frag); 2687 dwarf2_emit_insn (__is * 2); 2688 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 2689 fix_new_exp (frag_now, where, 2, 2690 &(op1.exp), FALSE, BFD_RELOC_MSP430X_S); 2691 } 2692 else 2693 { 2694 // mova z16(Rsrc), PC 2695 bin |= 0x0030 | op1.reg << 8; 2696 bfd_putl16 ((bfd_vma) bin, frag); 2697 dwarf2_emit_insn (__is * 2); 2698 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 2699 if (op1.reg == 0) 2700 // mova z16(PC), PC = mova TONI, PC 2701 fix_new_exp (frag_now, where, 2, 2702 &(op1.exp), TRUE, BFD_RELOC_MSP430X_PCREL_INDXD); 2703 else 2704 fix_new_exp (frag_now, where, 2, 2705 &(op1.exp), FALSE, BFD_RELOC_MSP430X_INDXD); 2706 } 2707 } 2708 else if (op1.mode == OP_EXP && op1.am == 3) 2709 { 2710 // mova #imm20, Rdst 2711 bin |= 0x0080; 2712 bfd_putl16 ((bfd_vma) bin, frag); 2713 dwarf2_emit_insn (__is * 2); 2714 bfd_putl16 ((bfd_vma) ZEROS, frag + 2); 2715 fix_new_exp (frag_now, where, 2, 2716 &(op1.exp), FALSE, BFD_RELOC_MSP430X_S); 2717 } 2718 else 2719 as_bad (_("source operand address mode not allowed with bra instruction")); 2720 } 2721 break; 2722 1794 2723 default: 1795 2724 as_bad (_("Illegal instruction or not implemented opcode.")); 1796 2725 } 1797 2726 1798 input_line_pointer = line ;2727 input_line_pointer = line + 1; // skip trailing zero 1799 2728 return 0; 1800 2729 } 1801 2730 1802 2731 void 1803 2732 md_assemble (char * str) 1804 2733 { 1805 struct msp430_opcode_s * opcode;2734 struct msp430_opcode_s const * opcode; 1806 2735 char cmd[32]; 1807 2736 unsigned int i = 0; 1808 2737 … … md_assemble (char * str) 1822 2751 return; 1823 2752 } 1824 2753 1825 opcode = (struct msp430_opcode_s *) hash_find (msp430_hash, cmd);2754 opcode = (struct msp430_opcode_s const *) hash_find (msp430_hash, cmd); 1826 2755 1827 2756 if (opcode == NULL) 1828 2757 { … … md_assemble (char * str) 1830 2759 return; 1831 2760 } 1832 2761 2762 if (msp430_core(msp430_mcu) < CORE_430X && opcode_format(opcode) >= FMT_X) 2763 { 2764 as_bad (_("Extended instruction (%s) not allowed with %s mcu"), opcode->name, msp430_mcu->name); 2765 return; 2766 } 2767 1833 2768 { 1834 2769 char *__t = input_line_pointer; 1835 2770 … … md_apply_fix (fixS * fixp, valueT * valuep, segT seg) 1964 2899 1965 2900 switch (fixp->fx_r_type) 1966 2901 { 2902 case BFD_RELOC_MSP430X_PCREL_D: 2903 case BFD_RELOC_MSP430X_PCREL_INDXD: 2904 value -= 2; // operand located 2 bytes after opcode 2905 break; 2906 case BFD_RELOC_MSP430X_PCREL_SRC: 2907 case BFD_RELOC_MSP430X_PCREL_SRC_BYTE: 2908 case BFD_RELOC_MSP430X_PCREL_DST: 2909 case BFD_RELOC_MSP430X_PCREL_DST_BYTE: 2910 value -= 4; // operand located 4 bytes after opcode 2911 break; 2912 case BFD_RELOC_MSP430X_PCREL_DST_2ND: 2913 case BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE: 2914 value -= 6; // operand located 6 bytes after opcode 2915 break; 2916 default: 2917 break; 2918 } 2919 2920 switch (fixp->fx_r_type) 2921 { 1967 2922 case BFD_RELOC_MSP430_10_PCREL: 1968 2923 if (value & 1) 1969 2924 as_bad_where (fixp->fx_file, fixp->fx_line, … … md_apply_fix (fixS * fixp, valueT * valuep, segT seg) 1988 2943 _("odd address operand: %ld"), value); 1989 2944 1990 2945 /* Nothing to be corrected here. */ 1991 if (value < -32768 || value > 6553 6)2946 if (value < -32768 || value > 65535) 1992 2947 as_bad_where (fixp->fx_file, fixp->fx_line, 1993 2948 _("operand out of range: %ld"), value); 1994 2949 … … md_apply_fix (fixS * fixp, valueT * valuep, segT seg) 1998 2953 1999 2954 case BFD_RELOC_MSP430_16_PCREL_BYTE: 2000 2955 /* Nothing to be corrected here. */ 2001 if (value < -32768 || value > 6553 6)2956 if (value < -32768 || value > 65535) 2002 2957 as_bad_where (fixp->fx_file, fixp->fx_line, 2003 2958 _("operand out of range: %ld"), value); 2004 2959 … … md_apply_fix (fixS * fixp, valueT * valuep, segT seg) 2017 2972 bfd_putl16 ((bfd_vma) value, where); 2018 2973 break; 2019 2974 2975 case BFD_RELOC_MSP430X_SRC: 2976 case BFD_RELOC_MSP430X_PCREL_SRC: 2977 if (value & 1) 2978 as_bad_where (fixp->fx_file, fixp->fx_line, 2979 _("odd operand: %ld"), value); 2980 case BFD_RELOC_MSP430X_SRC_BYTE: 2981 case BFD_RELOC_MSP430X_PCREL_SRC_BYTE: 2982 value &= 0xfffff; 2983 bfd_putl16 ((bfd_vma)(bfd_getl16 (where) & 0xf87f) | ((value >> 9) & 0x0780), where); 2984 /* 16 least-significant bits */ 2985 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4); 2986 break; 2987 case BFD_RELOC_MSP430X_DST: 2988 case BFD_RELOC_MSP430X_PCREL_DST: 2989 if (value & 1) 2990 as_bad_where (fixp->fx_file, fixp->fx_line, 2991 _("odd operand: %ld"), value); 2992 case BFD_RELOC_MSP430X_DST_BYTE: 2993 case BFD_RELOC_MSP430X_PCREL_DST_BYTE: 2994 bfd_putl16 ((bfd_vma)(bfd_getl16 (where) & 0xfff0) | ((value >> 16) & 0x000f), where); 2995 /* 16 least-significant bits */ 2996 value &= 0xfffff; 2997 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 4); 2998 break; 2999 case BFD_RELOC_MSP430X_DST_2ND: 3000 case BFD_RELOC_MSP430X_PCREL_DST_2ND: 3001 if (value & 1) 3002 as_bad_where (fixp->fx_file, fixp->fx_line, 3003 _("odd operand: %ld"), value); 3004 case BFD_RELOC_MSP430X_DST_2ND_BYTE: 3005 case BFD_RELOC_MSP430X_PCREL_DST_2ND_BYTE: 3006 value &= 0xfffff; 3007 bfd_putl16 ((bfd_vma)(bfd_getl16 (where) & 0xfff0) | ((value >> 16) & 0x000f), where); 3008 /* 16 least-significant bits */ 3009 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 6); 3010 break; 3011 case BFD_RELOC_MSP430X_S: 3012 if (value & 1) 3013 as_bad_where (fixp->fx_file, fixp->fx_line, 3014 _("odd operand: %ld"), value); 3015 case BFD_RELOC_MSP430X_S_BYTE: 3016 value &= 0xfffff; 3017 bfd_putl16 ((bfd_vma)(bfd_getl16 (where) & 0xf0ff) | ((value >> 8) & 0x0f00), where); 3018 /* 16 least-significant bits */ 3019 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2); 3020 break; 3021 case BFD_RELOC_MSP430X_D: 3022 case BFD_RELOC_MSP430X_PCREL_D: 3023 if (value & 1) 3024 as_bad_where (fixp->fx_file, fixp->fx_line, 3025 _("odd operand: %ld"), value); 3026 case BFD_RELOC_MSP430X_D_BYTE: 3027 value &= 0xfffff; 3028 bfd_putl16 ((bfd_vma)(bfd_getl16 (where) & 0xfff0) | ((value >> 16) & 0x000f), where); 3029 /* 16 least-significant bits */ 3030 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2); 3031 break; 3032 case BFD_RELOC_MSP430X_PCREL_INDXD: 3033 if (value & 1) 3034 as_bad_where (fixp->fx_file, fixp->fx_line, 3035 _("odd operand: %ld"), value); 3036 case BFD_RELOC_MSP430X_INDXD: 3037 if (value < -32768 || value > 65535) 3038 as_bad_where (fixp->fx_file, fixp->fx_line, 3039 _("operand out of range: %ld"), value); 3040 3041 value &= 0xffff; /* Get rid of extended sign. */ 3042 bfd_putl16 ((bfd_vma) value, where + 2); 3043 break; 3044 2020 3045 default: 2021 3046 as_fatal (_("line %d: unknown relocation type: 0x%x"), 2022 3047 fixp->fx_line, fixp->fx_r_type); -
include/elf/msp430.h
diff --git binutils-2.20.1.orig/include/elf/msp430.h binutils-2.20.1/include/elf/msp430.h index ff16ba2..8aeabdb 100644
old new 26 26 /* Processor specific flags for the ELF header e_flags field. */ 27 27 #define EF_MSP430_MACH 0xff 28 28 29 #define E_MSP430_MACH_MSP430x11 11 30 #define E_MSP430_MACH_MSP430x11x1 110 31 #define E_MSP430_MACH_MSP430x12 12 32 #define E_MSP430_MACH_MSP430x13 13 33 #define E_MSP430_MACH_MSP430x14 14 34 #define E_MSP430_MACH_MSP430x15 15 35 #define E_MSP430_MACH_MSP430x16 16 36 #define E_MSP430_MACH_MSP430x31 31 37 #define E_MSP430_MACH_MSP430x32 32 38 #define E_MSP430_MACH_MSP430x33 33 39 #define E_MSP430_MACH_MSP430x41 41 40 #define E_MSP430_MACH_MSP430x42 42 41 #define E_MSP430_MACH_MSP430x43 43 42 #define E_MSP430_MACH_MSP430x44 44 29 #define E_MSP430_MACH_MSP430x11 11 30 #define E_MSP430_MACH_MSP430x11x1 110 31 #define E_MSP430_MACH_MSP430x12 12 32 #define E_MSP430_MACH_MSP430x13 13 33 #define E_MSP430_MACH_MSP430x14 14 34 #define E_MSP430_MACH_MSP430x15 15 35 #define E_MSP430_MACH_MSP430x16 16 36 #define E_MSP430_MACH_MSP430x20 20 37 #define E_MSP430_MACH_MSP430x21 21 38 #define E_MSP430_MACH_MSP430x22 22 39 #define E_MSP430_MACH_MSP430x23 23 40 #define E_MSP430_MACH_MSP430x24 24 41 #define E_MSP430_MACH_MSP430x241 241 42 #define E_MSP430_MACH_MSP430x26 26 43 #define E_MSP430_MACH_MSP430x31 31 44 #define E_MSP430_MACH_MSP430x32 32 45 #define E_MSP430_MACH_MSP430x33 33 46 #define E_MSP430_MACH_MSP430x41 41 47 #define E_MSP430_MACH_MSP430x42 42 48 #define E_MSP430_MACH_MSP430x43 43 49 #define E_MSP430_MACH_MSP430x44 44 50 #define E_MSP430_MACH_MSP430x46 46 51 #define E_MSP430_MACH_MSP430x47 47 52 #define E_MSP430_MACH_MSP430x471 471 53 #define E_MSP430_MACH_MSP430x54 54 43 54 44 55 /* Relocations. */ 45 56 START_RELOC_NUMBERS (elf_msp430_reloc_type) … … START_RELOC_NUMBERS (elf_msp430_reloc_type) 52 63 RELOC_NUMBER (R_MSP430_16_PCREL_BYTE, 6) 53 64 RELOC_NUMBER (R_MSP430_2X_PCREL, 7) 54 65 RELOC_NUMBER (R_MSP430_RL_PCREL, 8) 66 RELOC_NUMBER (R_MSP430X_SRC_BYTE, 9) 67 RELOC_NUMBER (R_MSP430X_SRC, 10) 68 RELOC_NUMBER (R_MSP430X_DST_BYTE, 11) 69 RELOC_NUMBER (R_MSP430X_DST, 12) 70 RELOC_NUMBER (R_MSP430X_DST_2ND_BYTE, 13) 71 RELOC_NUMBER (R_MSP430X_DST_2ND, 14) 72 RELOC_NUMBER (R_MSP430X_PCREL_SRC_BYTE, 15) 73 RELOC_NUMBER (R_MSP430X_PCREL_SRC, 16) 74 RELOC_NUMBER (R_MSP430X_PCREL_DST_BYTE, 17) 75 RELOC_NUMBER (R_MSP430X_PCREL_DST, 18) 76 RELOC_NUMBER (R_MSP430X_PCREL_DST_2ND, 19) 77 RELOC_NUMBER (R_MSP430X_PCREL_DST_2ND_BYTE, 20) 78 RELOC_NUMBER (R_MSP430X_S_BYTE, 21) 79 RELOC_NUMBER (R_MSP430X_S, 22) 80 RELOC_NUMBER (R_MSP430X_D_BYTE, 23) 81 RELOC_NUMBER (R_MSP430X_D, 24) 82 RELOC_NUMBER (R_MSP430X_PCREL_D, 25) 83 RELOC_NUMBER (R_MSP430X_INDXD, 26) 84 RELOC_NUMBER (R_MSP430X_PCREL_INDXD, 27) 55 85 56 86 END_RELOC_NUMBERS (R_MSP430_max) 57 87 -
include/opcode/msp430.h
diff --git binutils-2.20.1.orig/include/opcode/msp430.h binutils-2.20.1/include/opcode/msp430.h index eec2f1e..58a8962 100644
old new struct msp430_operand_s 25 25 int ol; /* Operand length words. */ 26 26 int am; /* Addr mode. */ 27 27 int reg; /* Register. */ 28 int mode; /* Pperand mode. */28 int mode; /* Operand mode. */ 29 29 #define OP_REG 0 30 30 #define OP_EXP 1 31 31 #ifndef DASM_SECTION … … struct msp430_operand_s 33 33 #endif 34 34 }; 35 35 36 #define BYTE_OPERATION (1 << 6) /* Byte operation flag for all instructions. */ 36 #define BYTE_OPERATION (1 << 6) /* Byte operation flag for 430 instructions. */ 37 #define BYTE_OPERATION_X (1 << 22) /* Byte operation flag for 430x instructions. */ 38 #define NON_ADDR_OPERATION (1 << 6) /* Address operation flag for 430x instructions. */ 39 40 typedef enum 41 { 42 DEFAULT_OP, // instruction has no modifier 43 WORD_OP, // .w 44 BYTE_OP, // .b 45 ADDR_OP // .a 46 } 47 opwidth_t; 48 49 typedef enum 50 { 51 CORE_430, // 1xxx, 2xxx, 3xxx, 4xxx 52 CORE_430X, // 241x, 26xx, 46xx 53 CORE_430X2, // 5xxx 54 } 55 core_t; 56 57 typedef enum 58 { 59 FMT_EMULATED = 0, 60 FMT_DOUBLE_OPERAND, 61 FMT_SINGLE_OPERAND, 62 FMT_JUMP, 63 FMT_EMULATED_POLYMORPH_JUMP, 64 FMT_EMULATED_LONG_POLYMORPH_JUMP, 65 FMT_X_DOUBLE_OPERAND, 66 FMT_X_SINGLE_OPERAND, 67 FMT_X_EXCEPTION, 68 FMT_X_EMULATED, 69 FMT_X_ADDRESS, 70 71 FMT_X = FMT_X_DOUBLE_OPERAND, 72 FMT_MASK = 0x000f, 73 74 /* allowed modifiers: .b, .w, .a */ 75 MOD_NONE = 0, 76 MOD_W = 1 << 4, 77 MOD_B = 1 << 5, 78 MOD_A = 1 << 6, 79 MOD_MASK = 0x0070, 80 81 /* opcode variant */ 82 VAR_MASK = 0x0380, 83 } 84 format_t; 85 86 #define OP_V(x) (x << 7) 37 87 38 88 struct msp430_opcode_s 39 89 { 40 90 char *name; 41 int fmt; 42 int insn_opnumb; 43 int bin_opcode; 44 int bin_mask; 91 format_t fmt; 92 unsigned int insn_opnumb; 93 unsigned int bin_opcode; 94 unsigned int bin_mask; 95 }; 96 97 #define opcode_format(opcode) (opcode->fmt & FMT_MASK) 98 #define opcode_modifier(opcode) (opcode->fmt & MOD_MASK) 99 #define opcode_variant(opcode) ((opcode->fmt & VAR_MASK) >> 7) 100 101 /* opcode variants: */ 102 enum 103 { 104 V_NONE = 0, // ordinary instruction 105 106 /* FMT_EMULATED: */ 107 V_NOOP, // no operands: set/clear bit instructions, reti 108 V_SHIFT, // shift instructions 109 V_BR, // br instruction 110 111 /* FMT_SINGLE_OPERAND: */ 112 V_RETI = 1, // reti 113 V_CALL = 2, // hex operand in disassembly 114 115 /* FMT_X_SINGLE_OPERAND: */ 116 // V_NONE - #N operand disallowed 117 V_SWPSXT = 1, // #N operand disallowed, special A/L, B/W bits case with .a modifier 118 V_PUSHX, // #N operand allowed 119 120 /* FMT_X_EXCEPTIONS: */ 121 V_CALLA = 0, // calla 122 V_ROTM, // two operands, rotations 123 V_POPM, // two operands, popm 124 V_PUSHM, // two operands, pushm 125 126 /* FMT_X_EMULATED: */ 127 // V_NONE - substituted by 430x double operand instruction 128 V_X_SHIFT, // shifts 129 V_RETA, // reta, short instruction, no operands 130 V_EMU_ADDR, // substituted by address instruction other than mova 131 V_BRA, // bra, substituted by mova address instruction == format II exception instruction 132 // clra emulated by msp430 instruction 133 134 /* FMT_X_ADDRESS: */ 135 V_MOVA = 1, // mova, more address modes allowed 45 136 }; 46 137 47 #define MSP_INSN(name, size, numb, bin, mask) { #name, size,numb, bin, mask }138 #define MSP_INSN(name, format, opnumb, bin, mask) { #name, format, opnumb, bin, mask } 48 139 49 static struct msp430_opcode_s msp430_opcodes[] =140 static struct msp430_opcode_s const msp430_opcodes[] = 50 141 { 51 MSP_INSN (and, 1, 2, 0xf000, 0xf000), 52 MSP_INSN (inv, 0, 1, 0xe330, 0xfff0), 53 MSP_INSN (xor, 1, 2, 0xe000, 0xf000), 54 MSP_INSN (setz, 0, 0, 0xd322, 0xffff), 55 MSP_INSN (setc, 0, 0, 0xd312, 0xffff), 56 MSP_INSN (eint, 0, 0, 0xd232, 0xffff), 57 MSP_INSN (setn, 0, 0, 0xd222, 0xffff), 58 MSP_INSN (bis, 1, 2, 0xd000, 0xf000), 59 MSP_INSN (clrz, 0, 0, 0xc322, 0xffff), 60 MSP_INSN (clrc, 0, 0, 0xc312, 0xffff), 61 MSP_INSN (dint, 0, 0, 0xc232, 0xffff), 62 MSP_INSN (clrn, 0, 0, 0xc222, 0xffff), 63 MSP_INSN (bic, 1, 2, 0xc000, 0xf000), 64 MSP_INSN (bit, 1, 2, 0xb000, 0xf000), 65 MSP_INSN (dadc, 0, 1, 0xa300, 0xff30), 66 MSP_INSN (dadd, 1, 2, 0xa000, 0xf000), 67 MSP_INSN (tst, 0, 1, 0x9300, 0xff30), 68 MSP_INSN (cmp, 1, 2, 0x9000, 0xf000), 69 MSP_INSN (decd, 0, 1, 0x8320, 0xff30), 70 MSP_INSN (dec, 0, 1, 0x8310, 0xff30), 71 MSP_INSN (sub, 1, 2, 0x8000, 0xf000), 72 MSP_INSN (sbc, 0, 1, 0x7300, 0xff30), 73 MSP_INSN (subc, 1, 2, 0x7000, 0xf000), 74 MSP_INSN (adc, 0, 1, 0x6300, 0xff30), 75 MSP_INSN (rlc, 0, 2, 0x6000, 0xf000), 76 MSP_INSN (addc, 1, 2, 0x6000, 0xf000), 77 MSP_INSN (incd, 0, 1, 0x5320, 0xff30), 78 MSP_INSN (inc, 0, 1, 0x5310, 0xff30), 79 MSP_INSN (rla, 0, 2, 0x5000, 0xf000), 80 MSP_INSN (add, 1, 2, 0x5000, 0xf000), 81 MSP_INSN (nop, 0, 0, 0x4303, 0xffff), 82 MSP_INSN (clr, 0, 1, 0x4300, 0xff30), 83 MSP_INSN (ret, 0, 0, 0x4130, 0xff30), 84 MSP_INSN (pop, 0, 1, 0x4130, 0xff30), 85 MSP_INSN (br, 0, 3, 0x4000, 0xf000), 86 MSP_INSN (mov, 1, 2, 0x4000, 0xf000), 87 MSP_INSN (jmp, 3, 1, 0x3c00, 0xfc00), 88 MSP_INSN (jl, 3, 1, 0x3800, 0xfc00), 89 MSP_INSN (jge, 3, 1, 0x3400, 0xfc00), 90 MSP_INSN (jn, 3, 1, 0x3000, 0xfc00), 91 MSP_INSN (jc, 3, 1, 0x2c00, 0xfc00), 92 MSP_INSN (jhs, 3, 1, 0x2c00, 0xfc00), 93 MSP_INSN (jnc, 3, 1, 0x2800, 0xfc00), 94 MSP_INSN (jlo, 3, 1, 0x2800, 0xfc00), 95 MSP_INSN (jz, 3, 1, 0x2400, 0xfc00), 96 MSP_INSN (jeq, 3, 1, 0x2400, 0xfc00), 97 MSP_INSN (jnz, 3, 1, 0x2000, 0xfc00), 98 MSP_INSN (jne, 3, 1, 0x2000, 0xfc00), 99 MSP_INSN (reti, 2, 0, 0x1300, 0xffc0), 100 MSP_INSN (call, 2, 1, 0x1280, 0xffc0), 101 MSP_INSN (push, 2, 1, 0x1200, 0xff80), 102 MSP_INSN (sxt, 2, 1, 0x1180, 0xffc0), 103 MSP_INSN (rra, 2, 1, 0x1100, 0xff80), 104 MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0), 105 MSP_INSN (rrc, 2, 1, 0x1000, 0xff80), 142 MSP_INSN (and, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0xf000, 0xfffff000), 143 MSP_INSN (inv, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0xe330, 0xfffffff0), 144 MSP_INSN (xor, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0xe000, 0xfffff000), 145 MSP_INSN (setz, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xd322, 0xffffffff), 146 MSP_INSN (setc, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xd312, 0xffffffff), 147 MSP_INSN (eint, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xd232, 0xffffffff), 148 MSP_INSN (setn, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xd222, 0xffffffff), 149 MSP_INSN (bis, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0xd000, 0xfffff000), 150 MSP_INSN (clrz, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xc322, 0xffffffff), 151 MSP_INSN (clrc, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xc312, 0xffffffff), 152 MSP_INSN (dint, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xc232, 0xffffffff), 153 MSP_INSN (clrn, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0xc222, 0xffffffff), 154 MSP_INSN (bic, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0xc000, 0xfffff000), 155 MSP_INSN (bit, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0xb000, 0xfffff000), 156 MSP_INSN (dadc, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0xa300, 0xffffff30), 157 MSP_INSN (dadd, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0xa000, 0xfffff000), 158 MSP_INSN (tst, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x9300, 0xffffff30), 159 MSP_INSN (cmp, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0x9000, 0xfffff000), 160 MSP_INSN (decd, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x8320, 0xffffff30), 161 MSP_INSN (dec, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x8310, 0xffffff30), 162 MSP_INSN (sub, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0x8000, 0xfffff000), 163 MSP_INSN (sbc, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x7300, 0xffffff30), 164 MSP_INSN (subc, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0x7000, 0xfffff000), 165 MSP_INSN (adc, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x6300, 0xffffff30), 166 MSP_INSN (rlc, FMT_EMULATED | MOD_W|MOD_B | OP_V(V_SHIFT), 2, 0x6000, 0xfffff000), 167 MSP_INSN (addc, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0x6000, 0xfffff000), 168 MSP_INSN (incd, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x5320, 0xffffff30), 169 MSP_INSN (inc, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x5310, 0xffffff30), 170 MSP_INSN (rla, FMT_EMULATED | MOD_W|MOD_B | OP_V(V_SHIFT), 2, 0x5000, 0xfffff000), 171 MSP_INSN (add, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0x5000, 0xfffff000), 172 MSP_INSN (nop, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0x4303, 0xffffffff), 173 MSP_INSN (clr, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x4300, 0xffffff30), 174 MSP_INSN (clra, FMT_EMULATED | MOD_NONE | OP_V(0), 1, 0x4300, 0xffffff30), // MOV #0, Rdst 175 MSP_INSN (ret, FMT_EMULATED | MOD_NONE | OP_V(V_NOOP), 0, 0x4130, 0xffffffff), 176 MSP_INSN (pop, FMT_EMULATED | MOD_W|MOD_B | OP_V(0), 1, 0x4130, 0xffffff30), 177 MSP_INSN (br, FMT_EMULATED | MOD_NONE | OP_V(V_BR), 1, 0x4000, 0xfffff08f), 178 MSP_INSN (mov, FMT_DOUBLE_OPERAND | MOD_W|MOD_B | OP_V(0), 2, 0x4000, 0xfffff000), 179 180 MSP_INSN (jmp, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x3c00, 0xfffffc00), 181 MSP_INSN (jl, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x3800, 0xfffffc00), 182 MSP_INSN (jge, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x3400, 0xfffffc00), 183 MSP_INSN (jn, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x3000, 0xfffffc00), 184 MSP_INSN (jc, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2c00, 0xfffffc00), 185 MSP_INSN (jhs, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2c00, 0xfffffc00), 186 MSP_INSN (jnc, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2800, 0xfffffc00), 187 MSP_INSN (jlo, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2800, 0xfffffc00), 188 MSP_INSN (jz, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2400, 0xfffffc00), 189 MSP_INSN (jeq, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2400, 0xfffffc00), 190 MSP_INSN (jnz, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2000, 0xfffffc00), 191 MSP_INSN (jne, FMT_JUMP | MOD_NONE | OP_V(0), 1, 0x2000, 0xfffffc00), 192 193 MSP_INSN (reti, FMT_SINGLE_OPERAND | MOD_NONE | OP_V(V_RETI), 0, 0x1300, 0xffffffc0), 194 MSP_INSN (call, FMT_SINGLE_OPERAND | MOD_NONE | OP_V(V_CALL), 1, 0x1280, 0xffffffc0), 195 MSP_INSN (push, FMT_SINGLE_OPERAND | MOD_W|MOD_B | OP_V(0), 1, 0x1200, 0xffffff80), 196 MSP_INSN (sxt, FMT_SINGLE_OPERAND | MOD_NONE | OP_V(0), 1, 0x1180, 0xffffffc0), 197 MSP_INSN (rra, FMT_SINGLE_OPERAND | MOD_W|MOD_B | OP_V(0), 1, 0x1100, 0xffffff80), 198 MSP_INSN (swpb, FMT_SINGLE_OPERAND | MOD_NONE | OP_V(0), 1, 0x1080, 0xffffffc0), 199 MSP_INSN (rrc, FMT_SINGLE_OPERAND | MOD_W|MOD_B | OP_V(0), 1, 0x1000, 0xffffff80), 200 201 202 /* emulated instructions placed just before instruction emulated by for disassembly search */ 203 MSP_INSN (popx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x41301800, 0xff30f800), // MOVX @SP+, dst 204 MSP_INSN (clrx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x43001800, 0xff30f800), // MOVX #0, dst 205 MSP_INSN (movx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0x40001800, 0xf000f800), 206 MSP_INSN (incx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x53101800, 0xff30f800), // ADDX #1, dst 207 MSP_INSN (incdx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x53201800, 0xff30f800), // ADDX #2, dst 208 MSP_INSN (rlax, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(V_X_SHIFT), 1, 0x50001800, 0xf000f800), // ADDX dst, dst 209 MSP_INSN (addx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0x50001800, 0xf000f800), 210 MSP_INSN (adcx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x63001800, 0xff30f800), // ADDCX #0, dst 211 MSP_INSN (rlcx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(V_X_SHIFT), 1, 0x60001800, 0xf000f800), // ADDCX dst, dst 212 MSP_INSN (addcx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0x60001800, 0xf000f800), 213 MSP_INSN (sbcx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x73001800, 0xff30f800), // SUBCX #0, dst 214 MSP_INSN (subcx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0x70001800, 0xf000f800), 215 MSP_INSN (decx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x83101800, 0xff30f800), // SUBX #1, dst 216 MSP_INSN (decdx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x83201800, 0xff30f800), // SUBX #2, dst 217 MSP_INSN (subx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0x80001800, 0xf000f800), 218 MSP_INSN (tstx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x93001800, 0xff30f800), // CMPX #0, dst 219 MSP_INSN (cmpx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0x90001800, 0xf000f800), 220 MSP_INSN (dadcx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0xa3001800, 0xff30f800), // DADDX #0, dst 221 MSP_INSN (daddx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0xa0001800, 0xf000f800), 222 MSP_INSN (bitx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0xb0001800, 0xf000f800), 223 MSP_INSN (bicx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0xc0001800, 0xf000f800), 224 MSP_INSN (bisx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0xd0001800, 0xf000f800), 225 MSP_INSN (invx, FMT_X_EMULATED | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0xe3301800, 0xff30f800), // XORX #-1, dst 226 MSP_INSN (xorx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0xe0001800, 0xf000f800), 227 MSP_INSN (andx, FMT_X_DOUBLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 2, 0xf0001800, 0xf000f800), 228 229 MSP_INSN (rrcx, FMT_X_SINGLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x10001800, 0xff80f800), 230 MSP_INSN (swpbx, FMT_X_SINGLE_OPERAND | MOD_W|MOD_A | OP_V(V_SWPSXT), 1, 0x10801800, 0xffc0f800), 231 MSP_INSN (rrax, FMT_X_SINGLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(0), 1, 0x11001800, 0xff80f800), 232 MSP_INSN (sxtx, FMT_X_SINGLE_OPERAND | MOD_W|MOD_A | OP_V(V_SWPSXT), 1, 0x11801800, 0xffc0f800), 233 MSP_INSN (pushx, FMT_X_SINGLE_OPERAND | MOD_W|MOD_B|MOD_A | OP_V(V_PUSHX), 1, 0x12001800, 0xff80f800), 234 235 MSP_INSN (calla, FMT_X_EXCEPTION | MOD_NONE | OP_V(V_CALLA), 1, 0x1300, 0xffffff00), 236 MSP_INSN (pushm, FMT_X_EXCEPTION | MOD_W|MOD_A | OP_V(V_PUSHM), 2, 0x1400, 0xfffffe00), 237 MSP_INSN (popm, FMT_X_EXCEPTION | MOD_W|MOD_A | OP_V(V_POPM), 2, 0x1600, 0xfffffe00), 238 MSP_INSN (rrcm, FMT_X_EXCEPTION | MOD_W|MOD_A | OP_V(V_ROTM), 2, 0x0040, 0xfffff3e0), 239 MSP_INSN (rram, FMT_X_EXCEPTION | MOD_W|MOD_A | OP_V(V_ROTM), 2, 0x0140, 0xfffff3e0), 240 MSP_INSN (rlam, FMT_X_EXCEPTION | MOD_W|MOD_A | OP_V(V_ROTM), 2, 0x0240, 0xfffff3e0), 241 MSP_INSN (rrum, FMT_X_EXCEPTION | MOD_W|MOD_A | OP_V(V_ROTM), 2, 0x0340, 0xfffff3e0), 242 243 /* Address. */ 244 MSP_INSN (incda, FMT_X_EMULATED | MOD_NONE | OP_V(V_EMU_ADDR), 1, 0x03e0, 0xfffffff0), // ADDA #2, Rdst = ADDA R3, Rdst 245 MSP_INSN (adda, FMT_X_ADDRESS | MOD_NONE | OP_V(0), 2, 0x00a0, 0xfffff0b0), 246 MSP_INSN (tsta, FMT_X_EMULATED | MOD_NONE | OP_V(V_EMU_ADDR), 1, 0x03d0, 0xfffffff0), // CMPA #0, Rdst = CMPA R3, Rdst 247 MSP_INSN (cmpa, FMT_X_ADDRESS | MOD_NONE | OP_V(0), 2, 0x0090, 0xfffff0b0), 248 MSP_INSN (decda, FMT_X_EMULATED | MOD_NONE | OP_V(V_EMU_ADDR), 1, 0x03f0, 0xfffffff0), // SUBA #2, Rdst = SUBA R3, Rdst 249 MSP_INSN (suba, FMT_X_ADDRESS | MOD_NONE | OP_V(0), 2, 0x00b0, 0xfffff0b0), 250 MSP_INSN (reta, FMT_X_EMULATED | MOD_NONE | OP_V(V_RETA), 0, 0x0110, 0xffffffff), // MOVA @SP+, PC 251 MSP_INSN (bra, FMT_X_EMULATED | MOD_NONE | OP_V(V_BRA), 1, 0x0000, 0xfffff0cf), // MOVA dst, PC 252 MSP_INSN (bra, FMT_X_EMULATED | MOD_NONE | OP_V(V_BRA), 1, 0x0080, 0xfffff0bf), // MOVA #imm20, PC; MOVA Rsrc, Rdst 253 MSP_INSN (mova, FMT_X_ADDRESS | MOD_NONE | OP_V(V_MOVA), 1, 0x0000, 0xfffff000), 254 106 255 /* Simple polymorphs. */ 107 MSP_INSN (beq, 4, 0, 0, 0xffff), 108 MSP_INSN (bne, 4, 1, 0, 0xffff), 109 MSP_INSN (blt, 4, 2, 0, 0xffff), 110 MSP_INSN (bltu, 4, 3, 0, 0xffff), 111 MSP_INSN (bge, 4, 4, 0, 0xffff), 112 MSP_INSN (bgeu, 4, 5, 0, 0xffff), 113 MSP_INSN (bltn, 4, 6, 0, 0xffff), 114 MSP_INSN (jump, 4, 7, 0, 0xffff), 115 /* Long polymorphs. */ 116 MSP_INSN (bgt, 5, 0, 0, 0xffff), 117 MSP_INSN (bgtu, 5, 1, 0, 0xffff), 118 MSP_INSN (bleu, 5, 2, 0, 0xffff), 119 MSP_INSN (ble, 5, 3, 0, 0xffff), 256 MSP_INSN (beq, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(0), 1, 0, 0xffff), 257 MSP_INSN (bne, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(1), 1, 0, 0xffff), 258 MSP_INSN (blt, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(2), 1, 0, 0xffff), 259 MSP_INSN (bltu, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(3), 1, 0, 0xffff), 260 MSP_INSN (bge, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(4), 1, 0, 0xffff), 261 MSP_INSN (bgeu, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(5), 1, 0, 0xffff), 262 MSP_INSN (bltn, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(6), 1, 0, 0xffff), 263 MSP_INSN (jump, FMT_EMULATED_POLYMORPH_JUMP | MOD_NONE | OP_V(7), 1, 0, 0xffff), 120 264 265 /* Long polymorphs. */ 266 MSP_INSN (bgt, FMT_EMULATED_LONG_POLYMORPH_JUMP | MOD_NONE | OP_V(0), 1, 0, 0xffff), 267 MSP_INSN (bgtu, FMT_EMULATED_LONG_POLYMORPH_JUMP | MOD_NONE | OP_V(1), 1, 0, 0xffff), 268 MSP_INSN (bleu, FMT_EMULATED_LONG_POLYMORPH_JUMP | MOD_NONE | OP_V(2), 1, 0, 0xffff), 269 MSP_INSN (ble, FMT_EMULATED_LONG_POLYMORPH_JUMP | MOD_NONE | OP_V(3), 1, 0, 0xffff), 121 270 /* End of instruction set. */ 122 271 { NULL, 0, 0, 0, 0 } 123 272 }; -
ld/Makefile.am
diff --git binutils-2.20.1.orig/ld/Makefile.am binutils-2.20.1/ld/Makefile.am index d8bd1f9..fd26feb 100644
old new ALL_EMULATIONS = \ 198 198 eelf32mcore.o \ 199 199 eelf32mep.o \ 200 200 eelf32mb_linux.o \ 201 201 eelf32microblaze.o \ 202 202 eelf32mipswindiss.o \ 203 203 eelf32mt.o \ 204 204 eelf32openrisc.o \ … … ALL_EMULATIONS = \ 311 311 emsp430x147.o \ 312 312 emsp430x148.o \ 313 313 emsp430x149.o \ 314 emsp430x1471.o \ 315 emsp430x1481.o \ 316 emsp430x1491.o \ 314 317 emsp430x155.o \ 315 318 emsp430x156.o \ 316 319 emsp430x157.o \ … … ALL_EMULATIONS = \ 320 323 emsp430x1610.o \ 321 324 emsp430x1611.o \ 322 325 emsp430x1612.o \ 326 emsp430x2001.o \ 327 emsp430x2011.o \ 328 emsp430x2002.o \ 329 emsp430x2012.o \ 330 emsp430x2003.o \ 331 emsp430x2014.o \ 323 332 emsp430x2101.o \ 324 333 emsp430x2111.o \ 334 emsp430x2112.o \ 325 335 emsp430x2121.o \ 336 emsp430x2122.o \ 326 337 emsp430x2131.o \ 338 emsp430x2132.o \ 339 emsp430x2201.o \ 340 emsp430x2211.o \ 341 emsp430x2221.o \ 342 emsp430x2231.o \ 343 emsp430x2232.o \ 344 emsp430x2234.o \ 345 emsp430x2252.o \ 346 emsp430x2254.o \ 347 emsp430x2272.o \ 348 emsp430x2274.o \ 349 emsp430x233.o \ 350 emsp430x235.o \ 351 emsp430x2330.o \ 352 emsp430x2350.o \ 353 emsp430x2370.o \ 354 emsp430x247.o \ 355 emsp430x248.o \ 356 emsp430x249.o \ 357 emsp430x2410.o \ 358 emsp430x2471.o \ 359 emsp430x2481.o \ 360 emsp430x2491.o \ 361 emsp430x2416.o \ 362 emsp430x2417.o \ 363 emsp430x2418.o \ 364 emsp430x2419.o \ 365 emsp430x2616.o \ 366 emsp430x2617.o \ 367 emsp430x2618.o \ 368 emsp430x2619.o \ 327 369 emsp430x311.o \ 328 370 emsp430x312.o \ 329 371 emsp430x313.o \ … … ALL_EMULATIONS = \ 337 379 emsp430x413.o \ 338 380 emsp430x415.o \ 339 381 emsp430x417.o \ 382 emsp430x423.o \ 383 emsp430x425.o \ 384 emsp430x427.o \ 385 emsp430x4250.o \ 386 emsp430x4260.o \ 387 emsp430x4270.o \ 340 388 emsp430xE423.o \ 341 389 emsp430xE425.o \ 342 390 emsp430xE427.o \ 391 emsp430xE4232.o \ 392 emsp430xE4242.o \ 393 emsp430xE4252.o \ 394 emsp430xE4272.o \ 343 395 emsp430xW423.o \ 344 396 emsp430xW425.o \ 345 397 emsp430xW427.o \ 398 emsp430xG4250.o \ 399 emsp430xG4260.o \ 400 emsp430xG4270.o \ 346 401 emsp430xG437.o \ 347 402 emsp430xG438.o \ 348 403 emsp430xG439.o \ 349 404 emsp430x435.o \ 350 405 emsp430x436.o \ 351 406 emsp430x437.o \ 407 emsp430x4351.o \ 408 emsp430x4361.o \ 409 emsp430x4371.o \ 352 410 emsp430x447.o \ 353 411 emsp430x448.o \ 354 412 emsp430x449.o \ 413 emsp430xG4616.o \ 414 emsp430xG4617.o \ 415 emsp430xG4618.o \ 416 emsp430xG4619.o \ 417 emsp430x4783.o \ 418 emsp430x4784.o \ 419 emsp430x4793.o \ 420 emsp430x4794.o \ 421 emsp430x47166.o \ 422 emsp430x47176.o \ 423 emsp430x47186.o \ 424 emsp430x47196.o \ 425 emsp430x47167.o \ 426 emsp430x47177.o \ 427 emsp430x47187.o \ 428 emsp430x47197.o \ 429 emsp430x5418.o \ 430 emsp430x5419.o \ 431 emsp430x5435.o \ 432 emsp430x5436.o \ 433 emsp430x5437.o \ 434 emsp430x5438.o \ 435 emsp430x5510.o \ 436 emsp430x5513.o \ 437 emsp430x5514.o \ 438 emsp430x5515.o \ 439 emsp430x5517.o \ 440 emsp430x5519.o \ 441 emsp430x5521.o \ 442 emsp430x5522.o \ 443 emsp430x5524.o \ 444 emsp430x5525.o \ 445 emsp430x5526.o \ 446 emsp430x5527.o \ 447 emsp430x5528.o \ 448 emsp430x5529.o \ 449 emsp430x6638.o \ 450 ecc430x5133.o \ 451 ecc430x5125.o \ 452 ecc430x6125.o \ 453 ecc430x6135.o \ 454 ecc430x6126.o \ 455 ecc430x5137.o \ 456 ecc430x6127.o \ 457 ecc430x6137.o \ 355 458 enews.o \ 356 459 ens32knbsd.o \ 357 460 eor32.o \ … … emsp430x149.c: $(srcdir)/emulparams/msp430all.sh \ 1447 1550 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1448 1551 ${GEN_DEPENDS} 1449 1552 ${GENSCRIPTS} msp430x149 "$(tdir_msp430x149)" msp430all 1553 emsp430x1471.c: $(srcdir)/emulparams/msp430all.sh \ 1554 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1555 ${GEN_DEPENDS} 1556 ${GENSCRIPTS} msp430x1471 "$(tdir_msp430x1471)" msp430all 1557 emsp430x1481.c: $(srcdir)/emulparams/msp430all.sh \ 1558 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1559 ${GEN_DEPENDS} 1560 ${GENSCRIPTS} msp430x1481 "$(tdir_msp430x1481)" msp430all 1561 emsp430x1491.c: $(srcdir)/emulparams/msp430all.sh \ 1562 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1563 ${GEN_DEPENDS} 1564 ${GENSCRIPTS} msp430x1491 "$(tdir_msp430x1491)" msp430all 1450 1565 emsp430x155.c: $(srcdir)/emulparams/msp430all.sh \ 1451 1566 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1452 1567 ${GEN_DEPENDS} … … emsp430x1612.c: $(srcdir)/emulparams/msp430all.sh \ 1483 1598 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1484 1599 ${GEN_DEPENDS} 1485 1600 ${GENSCRIPTS} msp430x1612 "$(tdir_msp430x1612)" msp430all 1601 emsp430x2001.c: $(srcdir)/emulparams/msp430all.sh \ 1602 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1603 ${GEN_DEPENDS} 1604 ${GENSCRIPTS} msp430x2001 "$(tdir_msp430x2001)" msp430all 1605 emsp430x2011.c: $(srcdir)/emulparams/msp430all.sh \ 1606 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1607 ${GEN_DEPENDS} 1608 ${GENSCRIPTS} msp430x2011 "$(tdir_msp430x2011)" msp430all 1609 emsp430x2002.c: $(srcdir)/emulparams/msp430all.sh \ 1610 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1611 ${GEN_DEPENDS} 1612 ${GENSCRIPTS} msp430x2002 "$(tdir_msp430x2002)" msp430all 1613 emsp430x2012.c: $(srcdir)/emulparams/msp430all.sh \ 1614 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1615 ${GEN_DEPENDS} 1616 ${GENSCRIPTS} msp430x2012 "$(tdir_msp430x2012)" msp430all 1617 emsp430x2003.c: $(srcdir)/emulparams/msp430all.sh \ 1618 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1619 ${GEN_DEPENDS} 1620 ${GENSCRIPTS} msp430x2003 "$(tdir_msp430x2003)" msp430all 1621 emsp430x2013.c: $(srcdir)/emulparams/msp430all.sh \ 1622 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1623 ${GEN_DEPENDS} 1624 ${GENSCRIPTS} msp430x2013 "$(tdir_msp430x2013)" msp430all 1486 1625 emsp430x2101.c: $(srcdir)/emulparams/msp430all.sh \ 1487 1626 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1488 1627 ${GEN_DEPENDS} … … emsp430x2111.c: $(srcdir)/emulparams/msp430all.sh \ 1491 1630 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1492 1631 ${GEN_DEPENDS} 1493 1632 ${GENSCRIPTS} msp430x2111 "$(tdir_msp430x2111)" msp430all 1633 emsp430x2112.c: $(srcdir)/emulparams/msp430all.sh \ 1634 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1635 ${GEN_DEPENDS} 1636 ${GENSCRIPTS} msp430x2112 "$(tdir_msp430x2112)" msp430all 1494 1637 emsp430x2121.c: $(srcdir)/emulparams/msp430all.sh \ 1495 1638 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1496 1639 ${GEN_DEPENDS} 1497 1640 ${GENSCRIPTS} msp430x2121 "$(tdir_msp430x2121)" msp430all 1641 emsp430x2122.c: $(srcdir)/emulparams/msp430all.sh \ 1642 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1643 ${GEN_DEPENDS} 1644 ${GENSCRIPTS} msp430x2122 "$(tdir_msp430x2122)" msp430all 1498 1645 emsp430x2131.c: $(srcdir)/emulparams/msp430all.sh \ 1499 1646 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1500 1647 ${GEN_DEPENDS} 1501 1648 ${GENSCRIPTS} msp430x2131 "$(tdir_msp430x2131)" msp430all 1649 emsp430x2132.c: $(srcdir)/emulparams/msp430all.sh \ 1650 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1651 ${GEN_DEPENDS} 1652 ${GENSCRIPTS} msp430x2132 "$(tdir_msp430x2132)" msp430all 1653 emsp430x2201.c: $(srcdir)/emulparams/msp430all.sh \ 1654 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1655 ${GEN_DEPENDS} 1656 ${GENSCRIPTS} msp430x2201 "$(tdir_msp430x2201)" msp430all 1657 emsp430x2211.c: $(srcdir)/emulparams/msp430all.sh \ 1658 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1659 ${GEN_DEPENDS} 1660 ${GENSCRIPTS} msp430x2211 "$(tdir_msp430x2211)" msp430all 1661 emsp430x2221.c: $(srcdir)/emulparams/msp430all.sh \ 1662 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1663 ${GEN_DEPENDS} 1664 ${GENSCRIPTS} msp430x2221 "$(tdir_msp430x2221)" msp430all 1665 emsp430x2231.c: $(srcdir)/emulparams/msp430all.sh \ 1666 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1667 ${GEN_DEPENDS} 1668 ${GENSCRIPTS} msp430x2231 "$(tdir_msp430x2231)" msp430all 1669 emsp430x2232.c: $(srcdir)/emulparams/msp430all.sh \ 1670 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1671 ${GEN_DEPENDS} 1672 ${GENSCRIPTS} msp430x2232 "$(tdir_msp430x2232)" msp430all 1673 emsp430x2234.c: $(srcdir)/emulparams/msp430all.sh \ 1674 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1675 ${GEN_DEPENDS} 1676 ${GENSCRIPTS} msp430x2234 "$(tdir_msp430x2234)" msp430all 1677 emsp430x2252.c: $(srcdir)/emulparams/msp430all.sh \ 1678 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1679 ${GEN_DEPENDS} 1680 ${GENSCRIPTS} msp430x2252 "$(tdir_msp430x2252)" msp430all 1681 emsp430x2254.c: $(srcdir)/emulparams/msp430all.sh \ 1682 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1683 ${GEN_DEPENDS} 1684 ${GENSCRIPTS} msp430x2254 "$(tdir_msp430x2254)" msp430all 1685 emsp430x2272.c: $(srcdir)/emulparams/msp430all.sh \ 1686 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1687 ${GEN_DEPENDS} 1688 ${GENSCRIPTS} msp430x2272 "$(tdir_msp430x2272)" msp430all 1689 emsp430x2274.c: $(srcdir)/emulparams/msp430all.sh \ 1690 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1691 ${GEN_DEPENDS} 1692 ${GENSCRIPTS} msp430x2274 "$(tdir_msp430x2274)" msp430all 1693 emsp430x233.c: $(srcdir)/emulparams/msp430all.sh \ 1694 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1695 ${GEN_DEPENDS} 1696 ${GENSCRIPTS} msp430x233 "$(tdir_msp430x233)" msp430all 1697 emsp430x235.c: $(srcdir)/emulparams/msp430all.sh \ 1698 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1699 ${GEN_DEPENDS} 1700 ${GENSCRIPTS} msp430x235 "$(tdir_msp430x235)" msp430all 1701 emsp430x2330.c: $(srcdir)/emulparams/msp430all.sh \ 1702 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1703 ${GEN_DEPENDS} 1704 ${GENSCRIPTS} msp430x2330 "$(tdir_msp430x2330)" msp430all 1705 emsp430x2350.c: $(srcdir)/emulparams/msp430all.sh \ 1706 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1707 ${GEN_DEPENDS} 1708 ${GENSCRIPTS} msp430x2350 "$(tdir_msp430x2350)" msp430all 1709 emsp430x2370.c: $(srcdir)/emulparams/msp430all.sh \ 1710 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1711 ${GEN_DEPENDS} 1712 ${GENSCRIPTS} msp430x2370 "$(tdir_msp430x2370)" msp430all 1713 emsp430x247.c: $(srcdir)/emulparams/msp430all.sh \ 1714 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1715 ${GEN_DEPENDS} 1716 ${GENSCRIPTS} msp430x247 "$(tdir_msp430x247)" msp430all 1717 emsp430x248.c: $(srcdir)/emulparams/msp430all.sh \ 1718 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1719 ${GEN_DEPENDS} 1720 ${GENSCRIPTS} msp430x248 "$(tdir_msp430x248)" msp430all 1721 emsp430x249.c: $(srcdir)/emulparams/msp430all.sh \ 1722 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1723 ${GEN_DEPENDS} 1724 ${GENSCRIPTS} msp430x249 "$(tdir_msp430x249)" msp430all 1725 emsp430x2410.c: $(srcdir)/emulparams/msp430all.sh \ 1726 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1727 ${GEN_DEPENDS} 1728 ${GENSCRIPTS} msp430x2410 "$(tdir_msp430x2410)" msp430all 1729 emsp430x2471.c: $(srcdir)/emulparams/msp430all.sh \ 1730 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1731 ${GEN_DEPENDS} 1732 ${GENSCRIPTS} msp430x2471 "$(tdir_msp430x2471)" msp430all 1733 emsp430x2481.c: $(srcdir)/emulparams/msp430all.sh \ 1734 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1735 ${GEN_DEPENDS} 1736 ${GENSCRIPTS} msp430x2481 "$(tdir_msp430x2481)" msp430all 1737 emsp430x2491.c: $(srcdir)/emulparams/msp430all.sh \ 1738 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1739 ${GEN_DEPENDS} 1740 ${GENSCRIPTS} msp430x2491 "$(tdir_msp430x2491)" msp430all 1741 emsp430x2416.c: $(srcdir)/emulparams/msp430all.sh \ 1742 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1743 ${GEN_DEPENDS} 1744 ${GENSCRIPTS} msp430x2416 "$(tdir_msp430x2416)" msp430all 1745 emsp430x2417.c: $(srcdir)/emulparams/msp430all.sh \ 1746 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1747 ${GEN_DEPENDS} 1748 ${GENSCRIPTS} msp430x2417 "$(tdir_msp430x2417)" msp430all 1749 emsp430x2418.c: $(srcdir)/emulparams/msp430all.sh \ 1750 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1751 ${GEN_DEPENDS} 1752 ${GENSCRIPTS} msp430x2418 "$(tdir_msp430x2418)" msp430all 1753 emsp430x2419.c: $(srcdir)/emulparams/msp430all.sh \ 1754 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1755 ${GEN_DEPENDS} 1756 ${GENSCRIPTS} msp430x2419 "$(tdir_msp430x2419)" msp430all 1757 emsp430x2616.c: $(srcdir)/emulparams/msp430all.sh \ 1758 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1759 ${GEN_DEPENDS} 1760 ${GENSCRIPTS} msp430x2616 "$(tdir_msp430x2616)" msp430all 1761 emsp430x2617.c: $(srcdir)/emulparams/msp430all.sh \ 1762 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1763 ${GEN_DEPENDS} 1764 ${GENSCRIPTS} msp430x2617 "$(tdir_msp430x2617)" msp430all 1765 emsp430x2618.c: $(srcdir)/emulparams/msp430all.sh \ 1766 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1767 ${GEN_DEPENDS} 1768 ${GENSCRIPTS} msp430x2618 "$(tdir_msp430x2618)" msp430all 1769 emsp430x2619.c: $(srcdir)/emulparams/msp430all.sh \ 1770 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1771 ${GEN_DEPENDS} 1772 ${GENSCRIPTS} msp430x2619 "$(tdir_msp430x2619)" msp430all 1502 1773 emsp430x311.c: $(srcdir)/emulparams/msp430all.sh \ 1503 1774 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ 1504 1775 ${GEN_DEPENDS} … … emsp430x417.c: $(srcdir)/emulparams/msp430all.sh \ 1551 1822 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1552 1823 ${GEN_DEPENDS} 1553 1824 ${GENSCRIPTS} msp430x417 "$(tdir_msp430x417)" msp430all 1825 emsp430x423.c: $(srcdir)/emulparams/msp430all.sh \ 1826 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1827 ${GEN_DEPENDS} 1828 ${GENSCRIPTS} msp430x423 "$(tdir_msp430x423)" msp430all 1829 emsp430x425.c: $(srcdir)/emulparams/msp430all.sh \ 1830 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1831 ${GEN_DEPENDS} 1832 ${GENSCRIPTS} msp430x425 "$(tdir_msp430x425)" msp430all 1833 emsp430x427.c: $(srcdir)/emulparams/msp430all.sh \ 1834 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1835 ${GEN_DEPENDS} 1836 ${GENSCRIPTS} msp430x427 "$(tdir_msp430x427)" msp430all 1837 emsp430x4250.c: $(srcdir)/emulparams/msp430all.sh \ 1838 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1839 ${GEN_DEPENDS} 1840 ${GENSCRIPTS} msp430x4250 "$(tdir_msp430x4250)" msp430all 1841 emsp430x4260.c: $(srcdir)/emulparams/msp430all.sh \ 1842 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1843 ${GEN_DEPENDS} 1844 ${GENSCRIPTS} msp430x4260 "$(tdir_msp430x4260)" msp430all 1845 emsp430x4270.c: $(srcdir)/emulparams/msp430all.sh \ 1846 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1847 ${GEN_DEPENDS} 1848 ${GENSCRIPTS} msp430x4270 "$(tdir_msp430x4270)" msp430all 1849 emsp430xE4232.c: $(srcdir)/emulparams/msp430all.sh \ 1850 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1851 ${GEN_DEPENDS} 1852 ${GENSCRIPTS} msp430xE4232 "$(tdir_msp430xE4232)" msp430all 1853 emsp430xE4242.c: $(srcdir)/emulparams/msp430all.sh \ 1854 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1855 ${GEN_DEPENDS} 1856 ${GENSCRIPTS} msp430xE4242 "$(tdir_msp430xE4242)" msp430all 1857 emsp430xE4252.c: $(srcdir)/emulparams/msp430all.sh \ 1858 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1859 ${GEN_DEPENDS} 1860 ${GENSCRIPTS} msp430xE4252 "$(tdir_msp430xE4252)" msp430all 1861 emsp430xE4272.c: $(srcdir)/emulparams/msp430all.sh \ 1862 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1863 ${GEN_DEPENDS} 1864 ${GENSCRIPTS} msp430xE4272 "$(tdir_msp430xE4272)" msp430all 1554 1865 emsp430xE423.c: $(srcdir)/emulparams/msp430all.sh \ 1555 1866 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1556 1867 ${GEN_DEPENDS} … … emsp430xW427.c: $(srcdir)/emulparams/msp430all.sh \ 1575 1886 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1576 1887 ${GEN_DEPENDS} 1577 1888 ${GENSCRIPTS} msp430xW427 "$(tdir_msp430xW427)" msp430all 1889 emsp430xG4250.c: $(srcdir)/emulparams/msp430all.sh \ 1890 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1891 ${GEN_DEPENDS} 1892 ${GENSCRIPTS} msp430xG4250 "$(tdir_msp430xG4250)" msp430all 1893 emsp430xG4260.c: $(srcdir)/emulparams/msp430all.sh \ 1894 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1895 ${GEN_DEPENDS} 1896 ${GENSCRIPTS} msp430xG4260 "$(tdir_msp430xG4260)" msp430all 1897 emsp430xG4270.c: $(srcdir)/emulparams/msp430all.sh \ 1898 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1899 ${GEN_DEPENDS} 1900 ${GENSCRIPTS} msp430xG4270 "$(tdir_msp430xG4270)" msp430all 1578 1901 emsp430xG437.c: $(srcdir)/emulparams/msp430all.sh \ 1579 1902 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1580 1903 ${GEN_DEPENDS} … … emsp430x437.c: $(srcdir)/emulparams/msp430all.sh \ 1599 1922 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1600 1923 ${GEN_DEPENDS} 1601 1924 ${GENSCRIPTS} msp430x437 "$(tdir_msp430x437)" msp430all 1925 emsp430x4351.c: $(srcdir)/emulparams/msp430all.sh \ 1926 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1927 ${GEN_DEPENDS} 1928 ${GENSCRIPTS} msp430x4351 "$(tdir_msp430x4351)" msp430all 1929 emsp430x4361.c: $(srcdir)/emulparams/msp430all.sh \ 1930 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1931 ${GEN_DEPENDS} 1932 ${GENSCRIPTS} msp430x4361 "$(tdir_msp430x4361)" msp430all 1933 emsp430x4371.c: $(srcdir)/emulparams/msp430all.sh \ 1934 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1935 ${GEN_DEPENDS} 1936 ${GENSCRIPTS} msp430x4371 "$(tdir_msp430x4371)" msp430all 1602 1937 emsp430x447.c: $(srcdir)/emulparams/msp430all.sh \ 1603 1938 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1604 1939 ${GEN_DEPENDS} … … emsp430x449.c: $(srcdir)/emulparams/msp430all.sh \ 1611 1946 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1612 1947 ${GEN_DEPENDS} 1613 1948 ${GENSCRIPTS} msp430x449 "$(tdir_msp430x449)" msp430all 1949 emsp430xG4616.c: $(srcdir)/emulparams/msp430all.sh \ 1950 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1951 ${GEN_DEPENDS} 1952 ${GENSCRIPTS} msp430xG4616 "$(tdir_msp430xG4616)" msp430all 1953 emsp430xG4617.c: $(srcdir)/emulparams/msp430all.sh \ 1954 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1955 ${GEN_DEPENDS} 1956 ${GENSCRIPTS} msp430xG4617 "$(tdir_msp430xG4617)" msp430all 1957 emsp430xG4618.c: $(srcdir)/emulparams/msp430all.sh \ 1958 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1959 ${GEN_DEPENDS} 1960 ${GENSCRIPTS} msp430xG4618 "$(tdir_msp430xG4618)" msp430all 1961 emsp430xG4619.c: $(srcdir)/emulparams/msp430all.sh \ 1962 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1963 ${GEN_DEPENDS} 1964 ${GENSCRIPTS} msp430xG4619 "$(tdir_msp430xG4619)" msp430all 1965 emsp430x4783.c: $(srcdir)/emulparams/msp430all.sh \ 1966 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1967 ${GEN_DEPENDS} 1968 ${GENSCRIPTS} msp430x4783 "$(tdir_msp430x4783)" msp430all 1969 emsp430x4784.c: $(srcdir)/emulparams/msp430all.sh \ 1970 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1971 ${GEN_DEPENDS} 1972 ${GENSCRIPTS} msp430x4784 "$(tdir_msp430x4784)" msp430all 1973 emsp430x4793.c: $(srcdir)/emulparams/msp430all.sh \ 1974 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1975 ${GEN_DEPENDS} 1976 ${GENSCRIPTS} msp430x4793 "$(tdir_msp430x4793)" msp430all 1977 emsp430x4794.c: $(srcdir)/emulparams/msp430all.sh \ 1978 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1979 ${GEN_DEPENDS} 1980 ${GENSCRIPTS} msp430x4794 "$(tdir_msp430x4794)" msp430all 1981 emsp430x47166.c: $(srcdir)/emulparams/msp430all.sh \ 1982 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1983 ${GEN_DEPENDS} 1984 ${GENSCRIPTS} msp430x47166 "$(tdir_msp430x47166)" msp430all 1985 emsp430x47176.c: $(srcdir)/emulparams/msp430all.sh \ 1986 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1987 ${GEN_DEPENDS} 1988 ${GENSCRIPTS} msp430x47176 "$(tdir_msp430x47176)" msp430all 1989 emsp430x47186.c: $(srcdir)/emulparams/msp430all.sh \ 1990 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1991 ${GEN_DEPENDS} 1992 ${GENSCRIPTS} msp430x47186 "$(tdir_msp430x47186)" msp430all 1993 emsp430x47196.c: $(srcdir)/emulparams/msp430all.sh \ 1994 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1995 ${GEN_DEPENDS} 1996 ${GENSCRIPTS} msp430x47196 "$(tdir_msp430x47196)" msp430all 1997 emsp430x47167.c: $(srcdir)/emulparams/msp430all.sh \ 1998 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 1999 ${GEN_DEPENDS} 2000 ${GENSCRIPTS} msp430x47167 "$(tdir_msp430x47167)" msp430all 2001 emsp430x47177.c: $(srcdir)/emulparams/msp430all.sh \ 2002 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2003 ${GEN_DEPENDS} 2004 ${GENSCRIPTS} msp430x47177 "$(tdir_msp430x47177)" msp430all 2005 emsp430x47187.c: $(srcdir)/emulparams/msp430all.sh \ 2006 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2007 ${GEN_DEPENDS} 2008 ${GENSCRIPTS} msp430x47187 "$(tdir_msp430x47187)" msp430all 2009 emsp430x47197.c: $(srcdir)/emulparams/msp430all.sh \ 2010 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2011 ${GEN_DEPENDS} 2012 ${GENSCRIPTS} msp430x47197 "$(tdir_msp430x47197)" msp430all 2013 emsp430x5418.c: $(srcdir)/emulparams/msp430all.sh \ 2014 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2015 ${GEN_DEPENDS} 2016 ${GENSCRIPTS} msp430x5418 "$(tdir_msp430x5418)" msp430all 2017 emsp430x5419.c: $(srcdir)/emulparams/msp430all.sh \ 2018 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2019 ${GEN_DEPENDS} 2020 ${GENSCRIPTS} msp430x5419 "$(tdir_msp430x5419)" msp430all 2021 emsp430x5435.c: $(srcdir)/emulparams/msp430all.sh \ 2022 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2023 ${GEN_DEPENDS} 2024 ${GENSCRIPTS} msp430x5435 "$(tdir_msp430x5435)" msp430all 2025 emsp430x5436.c: $(srcdir)/emulparams/msp430all.sh \ 2026 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2027 ${GEN_DEPENDS} 2028 ${GENSCRIPTS} msp430x5436 "$(tdir_msp430x5436)" msp430all 2029 emsp430x5437.c: $(srcdir)/emulparams/msp430all.sh \ 2030 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2031 ${GEN_DEPENDS} 2032 ${GENSCRIPTS} msp430x5437 "$(tdir_msp430x5437)" msp430all 2033 emsp430x5438.c: $(srcdir)/emulparams/msp430all.sh \ 2034 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2035 ${GEN_DEPENDS} 2036 ${GENSCRIPTS} msp430x5438 "$(tdir_msp430x5438)" msp430all 2037 emsp430x5510.c: $(srcdir)/emulparams/msp430all.sh \ 2038 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2039 ${GEN_DEPENDS} 2040 ${GENSCRIPTS} msp430x5510 "$(tdir_msp430x5510)" msp430all 2041 emsp430x5513.c: $(srcdir)/emulparams/msp430all.sh \ 2042 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2043 ${GEN_DEPENDS} 2044 ${GENSCRIPTS} msp430x5513 "$(tdir_msp430x5513)" msp430all 2045 emsp430x5514.c: $(srcdir)/emulparams/msp430all.sh \ 2046 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2047 ${GEN_DEPENDS} 2048 ${GENSCRIPTS} msp430x5514 "$(tdir_msp430x5514)" msp430all 2049 emsp430x5515.c: $(srcdir)/emulparams/msp430all.sh \ 2050 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2051 ${GEN_DEPENDS} 2052 ${GENSCRIPTS} msp430x5515 "$(tdir_msp430x5515)" msp430all 2053 emsp430x5517.c: $(srcdir)/emulparams/msp430all.sh \ 2054 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2055 ${GEN_DEPENDS} 2056 ${GENSCRIPTS} msp430x5517 "$(tdir_msp430x5517)" msp430all 2057 emsp430x5519.c: $(srcdir)/emulparams/msp430all.sh \ 2058 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2059 ${GEN_DEPENDS} 2060 ${GENSCRIPTS} msp430x5519 "$(tdir_msp430x5519)" msp430all 2061 emsp430x5521.c: $(srcdir)/emulparams/msp430all.sh \ 2062 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2063 ${GEN_DEPENDS} 2064 ${GENSCRIPTS} msp430x5521 "$(tdir_msp430x5521)" msp430all 2065 emsp430x5522.c: $(srcdir)/emulparams/msp430all.sh \ 2066 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2067 ${GEN_DEPENDS} 2068 ${GENSCRIPTS} msp430x5522 "$(tdir_msp430x5522)" msp430all 2069 emsp430x5524.c: $(srcdir)/emulparams/msp430all.sh \ 2070 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2071 ${GEN_DEPENDS} 2072 ${GENSCRIPTS} msp430x5524 "$(tdir_msp430x5524)" msp430all 2073 emsp430x5525.c: $(srcdir)/emulparams/msp430all.sh \ 2074 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2075 ${GEN_DEPENDS} 2076 ${GENSCRIPTS} msp430x5525 "$(tdir_msp430x5525)" msp430all 2077 emsp430x5526.c: $(srcdir)/emulparams/msp430all.sh \ 2078 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2079 ${GEN_DEPENDS} 2080 ${GENSCRIPTS} msp430x5526 "$(tdir_msp430x5526)" msp430all 2081 emsp430x5527.c: $(srcdir)/emulparams/msp430all.sh \ 2082 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2083 ${GEN_DEPENDS} 2084 ${GENSCRIPTS} msp430x5527 "$(tdir_msp430x5527)" msp430all 2085 emsp430x5528.c: $(srcdir)/emulparams/msp430all.sh \ 2086 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2087 ${GEN_DEPENDS} 2088 ${GENSCRIPTS} msp430x5528 "$(tdir_msp430x5528)" msp430all 2089 emsp430x5529.c: $(srcdir)/emulparams/msp430all.sh \ 2090 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2091 ${GEN_DEPENDS} 2092 ${GENSCRIPTS} msp430x5529 "$(tdir_msp430x5529)" msp430all 2093 emsp430x6638.c: $(srcdir)/emulparams/msp430all.sh \ 2094 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2095 ${GEN_DEPENDS} 2096 ${GENSCRIPTS} msp430x6638 "$(tdir_msp430x6638)" msp430all 2097 ecc430x5133.c: $(srcdir)/emulparams/msp430all.sh \ 2098 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2099 ${GEN_DEPENDS} 2100 ${GENSCRIPTS} cc430x5133 "$(tdir_cc430x5133)" msp430all 2101 ecc430x5125.c: $(srcdir)/emulparams/msp430all.sh \ 2102 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2103 ${GEN_DEPENDS} 2104 ${GENSCRIPTS} cc430x5125 "$(tdir_cc430x5125)" msp430all 2105 ecc430x6125.c: $(srcdir)/emulparams/msp430all.sh \ 2106 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2107 ${GEN_DEPENDS} 2108 ${GENSCRIPTS} cc430x6125 "$(tdir_cc430x6125)" msp430all 2109 ecc430x6135.c: $(srcdir)/emulparams/msp430all.sh \ 2110 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2111 ${GEN_DEPENDS} 2112 ${GENSCRIPTS} cc430x6135 "$(tdir_cc430x6135)" msp430all 2113 ecc430x6126.c: $(srcdir)/emulparams/msp430all.sh \ 2114 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2115 ${GEN_DEPENDS} 2116 ${GENSCRIPTS} cc430x6126 "$(tdir_cc430x6126)" msp430all 2117 ecc430x5137.c: $(srcdir)/emulparams/msp430all.sh \ 2118 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2119 ${GEN_DEPENDS} 2120 ${GENSCRIPTS} cc430x5137 "$(tdir_cc430x5137)" msp430all 2121 ecc430x6127.c: $(srcdir)/emulparams/msp430all.sh \ 2122 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2123 ${GEN_DEPENDS} 2124 ${GENSCRIPTS} cc430x6127 "$(tdir_cc430x6127)" msp430all 2125 ecc430x6137.c: $(srcdir)/emulparams/msp430all.sh \ 2126 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2127 ${GEN_DEPENDS} 2128 ${GENSCRIPTS} cc430x6137 "$(tdir_cc430x6137)" msp430all 1614 2129 enews.c: $(srcdir)/emulparams/news.sh \ 1615 2130 $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} 1616 2131 ${GENSCRIPTS} news "$(tdir_news)" -
ld/Makefile.in
diff --git binutils-2.20.1.orig/ld/Makefile.in binutils-2.20.1/ld/Makefile.in index 3a8b4f5..48869d9 100644
old new ALL_EMULATIONS = \ 484 484 eelf32mcore.o \ 485 485 eelf32mep.o \ 486 486 eelf32mb_linux.o \ 487 487 eelf32microblaze.o \ 488 488 eelf32mipswindiss.o \ 489 489 eelf32mt.o \ 490 490 eelf32openrisc.o \ … … ALL_EMULATIONS = \ 597 597 emsp430x147.o \ 598 598 emsp430x148.o \ 599 599 emsp430x149.o \ 600 emsp430x1471.o \ 601 emsp430x1481.o \ 602 emsp430x1491.o \ 600 603 emsp430x155.o \ 601 604 emsp430x156.o \ 602 605 emsp430x157.o \ … … ALL_EMULATIONS = \ 606 609 emsp430x1610.o \ 607 610 emsp430x1611.o \ 608 611 emsp430x1612.o \ 612 emsp430x2001.o \ 613 emsp430x2011.o \ 614 emsp430x2002.o \ 615 emsp430x2012.o \ 616 emsp430x2003.o \ 617 emsp430x2014.o \ 609 618 emsp430x2101.o \ 610 619 emsp430x2111.o \ 620 emsp430x2112.o \ 611 621 emsp430x2121.o \ 622 emsp430x2122.o \ 612 623 emsp430x2131.o \ 624 emsp430x2132.o \ 625 emsp430x2201.o \ 626 emsp430x2211.o \ 627 emsp430x2221.o \ 628 emsp430x2231.o \ 629 emsp430x2232.o \ 630 emsp430x2234.o \ 631 emsp430x2252.o \ 632 emsp430x2254.o \ 633 emsp430x2272.o \ 634 emsp430x2274.o \ 635 emsp430x233.o \ 636 emsp430x235.o \ 637 emsp430x2330.o \ 638 emsp430x2350.o \ 639 emsp430x2370.o \ 640 emsp430x247.o \ 641 emsp430x248.o \ 642 emsp430x249.o \ 643 emsp430x2410.o \ 644 emsp430x2471.o \ 645 emsp430x2481.o \ 646 emsp430x2491.o \ 647 emsp430x2416.o \ 648 emsp430x2417.o \ 649 emsp430x2418.o \ 650 emsp430x2419.o \ 651 emsp430x2616.o \ 652 emsp430x2617.o \ 653 emsp430x2618.o \ 654 emsp430x2619.o \ 613 655 emsp430x311.o \ 614 656 emsp430x312.o \ 615 657 emsp430x313.o \ … … ALL_EMULATIONS = \ 623 665 emsp430x413.o \ 624 666 emsp430x415.o \ 625 667 emsp430x417.o \ 668 emsp430x423.o \ 669 emsp430x425.o \ 670 emsp430x427.o \ 671 emsp430x4250.o \ 672 emsp430x4260.o \ 673 emsp430x4270.o \ 626 674 emsp430xE423.o \ 627 675 emsp430xE425.o \ 628 676 emsp430xE427.o \ 677 emsp430xE4232.o \ 678 emsp430xE4242.o \ 679 emsp430xE4252.o \ 680 emsp430xE4272.o \ 629 681 emsp430xW423.o \ 630 682 emsp430xW425.o \ 631 683 emsp430xW427.o \ 684 emsp430xG4250.o \ 685 emsp430xG4260.o \ 686 emsp430xG4270.o \ 632 687 emsp430xG437.o \ 633 688 emsp430xG438.o \ 634 689 emsp430xG439.o \ 635 690 emsp430x435.o \ 636 691 emsp430x436.o \ 637 692 emsp430x437.o \ 693 emsp430x4351.o \ 694 emsp430x4361.o \ 695 emsp430x4371.o \ 638 696 emsp430x447.o \ 639 697 emsp430x448.o \ 640 698 emsp430x449.o \ 699 emsp430xG4616.o \ 700 emsp430xG4617.o \ 701 emsp430xG4618.o \ 702 emsp430xG4619.o \ 703 emsp430x4783.o \ 704 emsp430x4784.o \ 705 emsp430x4793.o \ 706 emsp430x4794.o \ 707 emsp430x47166.o \ 708 emsp430x47176.o \ 709 emsp430x47186.o \ 710 emsp430x47196.o \ 711 emsp430x47167.o \ 712 emsp430x47177.o \ 713 emsp430x47187.o \ 714 emsp430x47197.o \ 715 emsp430x5418.o \ 716 emsp430x5419.o \ 717 emsp430x5435.o \ 718 emsp430x5436.o \ 719 emsp430x5437.o \ 720 emsp430x5438.o \ 721 emsp430x5510.o \ 722 emsp430x5513.o \ 723 emsp430x5514.o \ 724 emsp430x5515.o \ 725 emsp430x5517.o \ 726 emsp430x5519.o \ 727 emsp430x5521.o \ 728 emsp430x5522.o \ 729 emsp430x5524.o \ 730 emsp430x5525.o \ 731 emsp430x5526.o \ 732 emsp430x5527.o \ 733 emsp430x5528.o \ 734 emsp430x5529.o \ 735 emsp430x6638.o \ 736 ecc430x5133.o \ 737 ecc430x5125.o \ 738 ecc430x6125.o \ 739 ecc430x6135.o \ 740 ecc430x6126.o \ 741 ecc430x5137.o \ 742 ecc430x6127.o \ 743 ecc430x6137.o \ 641 744 enews.o \ 642 745 ens32knbsd.o \ 643 746 eor32.o \ … … emsp430x149.c: $(srcdir)/emulparams/msp430all.sh \ 2789 2892 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2790 2893 ${GEN_DEPENDS} 2791 2894 ${GENSCRIPTS} msp430x149 "$(tdir_msp430x149)" msp430all 2895 emsp430x1471.c: $(srcdir)/emulparams/msp430all.sh \ 2896 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2897 ${GEN_DEPENDS} 2898 ${GENSCRIPTS} msp430x1471 "$(tdir_msp430x1471)" msp430all 2899 emsp430x1481.c: $(srcdir)/emulparams/msp430all.sh \ 2900 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2901 ${GEN_DEPENDS} 2902 ${GENSCRIPTS} msp430x1481 "$(tdir_msp430x1481)" msp430all 2903 emsp430x1491.c: $(srcdir)/emulparams/msp430all.sh \ 2904 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2905 ${GEN_DEPENDS} 2906 ${GENSCRIPTS} msp430x1491 "$(tdir_msp430x1491)" msp430all 2792 2907 emsp430x155.c: $(srcdir)/emulparams/msp430all.sh \ 2793 2908 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2794 2909 ${GEN_DEPENDS} … … emsp430x1612.c: $(srcdir)/emulparams/msp430all.sh \ 2825 2940 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2826 2941 ${GEN_DEPENDS} 2827 2942 ${GENSCRIPTS} msp430x1612 "$(tdir_msp430x1612)" msp430all 2943 emsp430x2001.c: $(srcdir)/emulparams/msp430all.sh \ 2944 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2945 ${GEN_DEPENDS} 2946 ${GENSCRIPTS} msp430x2001 "$(tdir_msp430x2001)" msp430all 2947 emsp430x2011.c: $(srcdir)/emulparams/msp430all.sh \ 2948 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2949 ${GEN_DEPENDS} 2950 ${GENSCRIPTS} msp430x2011 "$(tdir_msp430x2011)" msp430all 2951 emsp430x2002.c: $(srcdir)/emulparams/msp430all.sh \ 2952 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2953 ${GEN_DEPENDS} 2954 ${GENSCRIPTS} msp430x2002 "$(tdir_msp430x2002)" msp430all 2955 emsp430x2012.c: $(srcdir)/emulparams/msp430all.sh \ 2956 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2957 ${GEN_DEPENDS} 2958 ${GENSCRIPTS} msp430x2012 "$(tdir_msp430x2012)" msp430all 2959 emsp430x2003.c: $(srcdir)/emulparams/msp430all.sh \ 2960 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2961 ${GEN_DEPENDS} 2962 ${GENSCRIPTS} msp430x2003 "$(tdir_msp430x2003)" msp430all 2963 emsp430x2013.c: $(srcdir)/emulparams/msp430all.sh \ 2964 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2965 ${GEN_DEPENDS} 2966 ${GENSCRIPTS} msp430x2013 "$(tdir_msp430x2013)" msp430all 2828 2967 emsp430x2101.c: $(srcdir)/emulparams/msp430all.sh \ 2829 2968 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2830 2969 ${GEN_DEPENDS} … … emsp430x2111.c: $(srcdir)/emulparams/msp430all.sh \ 2833 2972 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2834 2973 ${GEN_DEPENDS} 2835 2974 ${GENSCRIPTS} msp430x2111 "$(tdir_msp430x2111)" msp430all 2975 emsp430x2112.c: $(srcdir)/emulparams/msp430all.sh \ 2976 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2977 ${GEN_DEPENDS} 2978 ${GENSCRIPTS} msp430x2112 "$(tdir_msp430x2112)" msp430all 2836 2979 emsp430x2121.c: $(srcdir)/emulparams/msp430all.sh \ 2837 2980 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2838 2981 ${GEN_DEPENDS} 2839 2982 ${GENSCRIPTS} msp430x2121 "$(tdir_msp430x2121)" msp430all 2983 emsp430x2122.c: $(srcdir)/emulparams/msp430all.sh \ 2984 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2985 ${GEN_DEPENDS} 2986 ${GENSCRIPTS} msp430x2122 "$(tdir_msp430x2122)" msp430all 2840 2987 emsp430x2131.c: $(srcdir)/emulparams/msp430all.sh \ 2841 2988 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2842 2989 ${GEN_DEPENDS} 2843 2990 ${GENSCRIPTS} msp430x2131 "$(tdir_msp430x2131)" msp430all 2991 emsp430x2132.c: $(srcdir)/emulparams/msp430all.sh \ 2992 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2993 ${GEN_DEPENDS} 2994 ${GENSCRIPTS} msp430x2132 "$(tdir_msp430x2132)" msp430all 2995 emsp430x2201.c: $(srcdir)/emulparams/msp430all.sh \ 2996 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2997 ${GEN_DEPENDS} 2998 ${GENSCRIPTS} msp430x2201 "$(tdir_msp430x2201)" msp430all 2999 emsp430x2211.c: $(srcdir)/emulparams/msp430all.sh \ 3000 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3001 ${GEN_DEPENDS} 3002 ${GENSCRIPTS} msp430x2211 "$(tdir_msp430x2211)" msp430all 3003 emsp430x2221.c: $(srcdir)/emulparams/msp430all.sh \ 3004 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3005 ${GEN_DEPENDS} 3006 ${GENSCRIPTS} msp430x2221 "$(tdir_msp430x2221)" msp430all 3007 emsp430x2231.c: $(srcdir)/emulparams/msp430all.sh \ 3008 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3009 ${GEN_DEPENDS} 3010 ${GENSCRIPTS} msp430x2231 "$(tdir_msp430x2231)" msp430all 3011 emsp430x2232.c: $(srcdir)/emulparams/msp430all.sh \ 3012 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3013 ${GEN_DEPENDS} 3014 ${GENSCRIPTS} msp430x2232 "$(tdir_msp430x2232)" msp430all 3015 emsp430x2234.c: $(srcdir)/emulparams/msp430all.sh \ 3016 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3017 ${GEN_DEPENDS} 3018 ${GENSCRIPTS} msp430x2234 "$(tdir_msp430x2234)" msp430all 3019 emsp430x2252.c: $(srcdir)/emulparams/msp430all.sh \ 3020 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3021 ${GEN_DEPENDS} 3022 ${GENSCRIPTS} msp430x2252 "$(tdir_msp430x2252)" msp430all 3023 emsp430x2254.c: $(srcdir)/emulparams/msp430all.sh \ 3024 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3025 ${GEN_DEPENDS} 3026 ${GENSCRIPTS} msp430x2254 "$(tdir_msp430x2254)" msp430all 3027 emsp430x2272.c: $(srcdir)/emulparams/msp430all.sh \ 3028 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3029 ${GEN_DEPENDS} 3030 ${GENSCRIPTS} msp430x2272 "$(tdir_msp430x2272)" msp430all 3031 emsp430x2274.c: $(srcdir)/emulparams/msp430all.sh \ 3032 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3033 ${GEN_DEPENDS} 3034 ${GENSCRIPTS} msp430x2274 "$(tdir_msp430x2274)" msp430all 3035 emsp430x233.c: $(srcdir)/emulparams/msp430all.sh \ 3036 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3037 ${GEN_DEPENDS} 3038 ${GENSCRIPTS} msp430x233 "$(tdir_msp430x233)" msp430all 3039 emsp430x235.c: $(srcdir)/emulparams/msp430all.sh \ 3040 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3041 ${GEN_DEPENDS} 3042 ${GENSCRIPTS} msp430x235 "$(tdir_msp430x235)" msp430all 3043 emsp430x2330.c: $(srcdir)/emulparams/msp430all.sh \ 3044 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3045 ${GEN_DEPENDS} 3046 ${GENSCRIPTS} msp430x2330 "$(tdir_msp430x2330)" msp430all 3047 emsp430x2350.c: $(srcdir)/emulparams/msp430all.sh \ 3048 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3049 ${GEN_DEPENDS} 3050 ${GENSCRIPTS} msp430x2350 "$(tdir_msp430x2350)" msp430all 3051 emsp430x2370.c: $(srcdir)/emulparams/msp430all.sh \ 3052 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3053 ${GEN_DEPENDS} 3054 ${GENSCRIPTS} msp430x2370 "$(tdir_msp430x2370)" msp430all 3055 emsp430x247.c: $(srcdir)/emulparams/msp430all.sh \ 3056 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3057 ${GEN_DEPENDS} 3058 ${GENSCRIPTS} msp430x247 "$(tdir_msp430x247)" msp430all 3059 emsp430x248.c: $(srcdir)/emulparams/msp430all.sh \ 3060 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3061 ${GEN_DEPENDS} 3062 ${GENSCRIPTS} msp430x248 "$(tdir_msp430x248)" msp430all 3063 emsp430x249.c: $(srcdir)/emulparams/msp430all.sh \ 3064 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3065 ${GEN_DEPENDS} 3066 ${GENSCRIPTS} msp430x249 "$(tdir_msp430x249)" msp430all 3067 emsp430x2410.c: $(srcdir)/emulparams/msp430all.sh \ 3068 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3069 ${GEN_DEPENDS} 3070 ${GENSCRIPTS} msp430x2410 "$(tdir_msp430x2410)" msp430all 3071 emsp430x2471.c: $(srcdir)/emulparams/msp430all.sh \ 3072 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3073 ${GEN_DEPENDS} 3074 ${GENSCRIPTS} msp430x2471 "$(tdir_msp430x2471)" msp430all 3075 emsp430x2481.c: $(srcdir)/emulparams/msp430all.sh \ 3076 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3077 ${GEN_DEPENDS} 3078 ${GENSCRIPTS} msp430x2481 "$(tdir_msp430x2481)" msp430all 3079 emsp430x2491.c: $(srcdir)/emulparams/msp430all.sh \ 3080 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3081 ${GEN_DEPENDS} 3082 ${GENSCRIPTS} msp430x2491 "$(tdir_msp430x2491)" msp430all 3083 emsp430x2416.c: $(srcdir)/emulparams/msp430all.sh \ 3084 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3085 ${GEN_DEPENDS} 3086 ${GENSCRIPTS} msp430x2416 "$(tdir_msp430x2416)" msp430all 3087 emsp430x2417.c: $(srcdir)/emulparams/msp430all.sh \ 3088 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3089 ${GEN_DEPENDS} 3090 ${GENSCRIPTS} msp430x2417 "$(tdir_msp430x2417)" msp430all 3091 emsp430x2418.c: $(srcdir)/emulparams/msp430all.sh \ 3092 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3093 ${GEN_DEPENDS} 3094 ${GENSCRIPTS} msp430x2418 "$(tdir_msp430x2418)" msp430all 3095 emsp430x2419.c: $(srcdir)/emulparams/msp430all.sh \ 3096 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3097 ${GEN_DEPENDS} 3098 ${GENSCRIPTS} msp430x2419 "$(tdir_msp430x2419)" msp430all 3099 emsp430x2616.c: $(srcdir)/emulparams/msp430all.sh \ 3100 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3101 ${GEN_DEPENDS} 3102 ${GENSCRIPTS} msp430x2616 "$(tdir_msp430x2616)" msp430all 3103 emsp430x2617.c: $(srcdir)/emulparams/msp430all.sh \ 3104 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3105 ${GEN_DEPENDS} 3106 ${GENSCRIPTS} msp430x2617 "$(tdir_msp430x2617)" msp430all 3107 emsp430x2618.c: $(srcdir)/emulparams/msp430all.sh \ 3108 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3109 ${GEN_DEPENDS} 3110 ${GENSCRIPTS} msp430x2618 "$(tdir_msp430x2618)" msp430all 3111 emsp430x2619.c: $(srcdir)/emulparams/msp430all.sh \ 3112 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3113 ${GEN_DEPENDS} 3114 ${GENSCRIPTS} msp430x2619 "$(tdir_msp430x2619)" msp430all 2844 3115 emsp430x311.c: $(srcdir)/emulparams/msp430all.sh \ 2845 3116 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ 2846 3117 ${GEN_DEPENDS} … … emsp430x417.c: $(srcdir)/emulparams/msp430all.sh \ 2893 3164 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2894 3165 ${GEN_DEPENDS} 2895 3166 ${GENSCRIPTS} msp430x417 "$(tdir_msp430x417)" msp430all 3167 emsp430x423.c: $(srcdir)/emulparams/msp430all.sh \ 3168 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3169 ${GEN_DEPENDS} 3170 ${GENSCRIPTS} msp430x423 "$(tdir_msp430x423)" msp430all 3171 emsp430x425.c: $(srcdir)/emulparams/msp430all.sh \ 3172 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3173 ${GEN_DEPENDS} 3174 ${GENSCRIPTS} msp430x425 "$(tdir_msp430x425)" msp430all 3175 emsp430x427.c: $(srcdir)/emulparams/msp430all.sh \ 3176 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3177 ${GEN_DEPENDS} 3178 ${GENSCRIPTS} msp430x427 "$(tdir_msp430x427)" msp430all 3179 emsp430x4250.c: $(srcdir)/emulparams/msp430all.sh \ 3180 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3181 ${GEN_DEPENDS} 3182 ${GENSCRIPTS} msp430x4250 "$(tdir_msp430x4250)" msp430all 3183 emsp430x4260.c: $(srcdir)/emulparams/msp430all.sh \ 3184 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3185 ${GEN_DEPENDS} 3186 ${GENSCRIPTS} msp430x4260 "$(tdir_msp430x4260)" msp430all 3187 emsp430x4270.c: $(srcdir)/emulparams/msp430all.sh \ 3188 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3189 ${GEN_DEPENDS} 3190 ${GENSCRIPTS} msp430x4270 "$(tdir_msp430x4270)" msp430all 3191 emsp430xE4232.c: $(srcdir)/emulparams/msp430all.sh \ 3192 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3193 ${GEN_DEPENDS} 3194 ${GENSCRIPTS} msp430xE4232 "$(tdir_msp430xE4232)" msp430all 3195 emsp430xE4242.c: $(srcdir)/emulparams/msp430all.sh \ 3196 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3197 ${GEN_DEPENDS} 3198 ${GENSCRIPTS} msp430xE4242 "$(tdir_msp430xE4242)" msp430all 3199 emsp430xE4252.c: $(srcdir)/emulparams/msp430all.sh \ 3200 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3201 ${GEN_DEPENDS} 3202 ${GENSCRIPTS} msp430xE4252 "$(tdir_msp430xE4252)" msp430all 3203 emsp430xE4272.c: $(srcdir)/emulparams/msp430all.sh \ 3204 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3205 ${GEN_DEPENDS} 3206 ${GENSCRIPTS} msp430xE4272 "$(tdir_msp430xE4272)" msp430all 2896 3207 emsp430xE423.c: $(srcdir)/emulparams/msp430all.sh \ 2897 3208 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2898 3209 ${GEN_DEPENDS} … … emsp430xW427.c: $(srcdir)/emulparams/msp430all.sh \ 2917 3228 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2918 3229 ${GEN_DEPENDS} 2919 3230 ${GENSCRIPTS} msp430xW427 "$(tdir_msp430xW427)" msp430all 3231 emsp430xG4250.c: $(srcdir)/emulparams/msp430all.sh \ 3232 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3233 ${GEN_DEPENDS} 3234 ${GENSCRIPTS} msp430xG4250 "$(tdir_msp430xG4250)" msp430all 3235 emsp430xG4260.c: $(srcdir)/emulparams/msp430all.sh \ 3236 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3237 ${GEN_DEPENDS} 3238 ${GENSCRIPTS} msp430xG4260 "$(tdir_msp430xG4260)" msp430all 3239 emsp430xG4270.c: $(srcdir)/emulparams/msp430all.sh \ 3240 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3241 ${GEN_DEPENDS} 3242 ${GENSCRIPTS} msp430xG4270 "$(tdir_msp430xG4270)" msp430all 2920 3243 emsp430xG437.c: $(srcdir)/emulparams/msp430all.sh \ 2921 3244 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2922 3245 ${GEN_DEPENDS} … … emsp430x437.c: $(srcdir)/emulparams/msp430all.sh \ 2941 3264 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2942 3265 ${GEN_DEPENDS} 2943 3266 ${GENSCRIPTS} msp430x437 "$(tdir_msp430x437)" msp430all 3267 emsp430x4351.c: $(srcdir)/emulparams/msp430all.sh \ 3268 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3269 ${GEN_DEPENDS} 3270 ${GENSCRIPTS} msp430x4351 "$(tdir_msp430x4351)" msp430all 3271 emsp430x4361.c: $(srcdir)/emulparams/msp430all.sh \ 3272 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3273 ${GEN_DEPENDS} 3274 ${GENSCRIPTS} msp430x4361 "$(tdir_msp430x4361)" msp430all 3275 emsp430x4371.c: $(srcdir)/emulparams/msp430all.sh \ 3276 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3277 ${GEN_DEPENDS} 3278 ${GENSCRIPTS} msp430x4371 "$(tdir_msp430x4371)" msp430all 2944 3279 emsp430x447.c: $(srcdir)/emulparams/msp430all.sh \ 2945 3280 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2946 3281 ${GEN_DEPENDS} … … emsp430x449.c: $(srcdir)/emulparams/msp430all.sh \ 2953 3288 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 2954 3289 ${GEN_DEPENDS} 2955 3290 ${GENSCRIPTS} msp430x449 "$(tdir_msp430x449)" msp430all 3291 emsp430xG4616.c: $(srcdir)/emulparams/msp430all.sh \ 3292 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3293 ${GEN_DEPENDS} 3294 ${GENSCRIPTS} msp430xG4616 "$(tdir_msp430xG4616)" msp430all 3295 emsp430xG4617.c: $(srcdir)/emulparams/msp430all.sh \ 3296 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3297 ${GEN_DEPENDS} 3298 ${GENSCRIPTS} msp430xG4617 "$(tdir_msp430xG4617)" msp430all 3299 emsp430xG4618.c: $(srcdir)/emulparams/msp430all.sh \ 3300 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3301 ${GEN_DEPENDS} 3302 ${GENSCRIPTS} msp430xG4618 "$(tdir_msp430xG4618)" msp430all 3303 emsp430xG4619.c: $(srcdir)/emulparams/msp430all.sh \ 3304 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3305 ${GEN_DEPENDS} 3306 ${GENSCRIPTS} msp430xG4619 "$(tdir_msp430xG4619)" msp430all 3307 emsp430x4783.c: $(srcdir)/emulparams/msp430all.sh \ 3308 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3309 ${GEN_DEPENDS} 3310 ${GENSCRIPTS} msp430x4783 "$(tdir_msp430x4783)" msp430all 3311 emsp430x4784.c: $(srcdir)/emulparams/msp430all.sh \ 3312 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3313 ${GEN_DEPENDS} 3314 ${GENSCRIPTS} msp430x4784 "$(tdir_msp430x4784)" msp430all 3315 emsp430x4793.c: $(srcdir)/emulparams/msp430all.sh \ 3316 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3317 ${GEN_DEPENDS} 3318 ${GENSCRIPTS} msp430x4793 "$(tdir_msp430x4793)" msp430all 3319 emsp430x4794.c: $(srcdir)/emulparams/msp430all.sh \ 3320 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3321 ${GEN_DEPENDS} 3322 ${GENSCRIPTS} msp430x4794 "$(tdir_msp430x4794)" msp430all 3323 emsp430x5418.c: $(srcdir)/emulparams/msp430all.sh \ 3324 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3325 ${GEN_DEPENDS} 3326 ${GENSCRIPTS} msp430x5418 "$(tdir_msp430x5418)" msp430all 3327 emsp430x47166.c: $(srcdir)/emulparams/msp430all.sh \ 3328 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3329 ${GEN_DEPENDS} 3330 ${GENSCRIPTS} msp430x47166 "$(tdir_msp430x47166)" msp430all 3331 emsp430x47176.c: $(srcdir)/emulparams/msp430all.sh \ 3332 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3333 ${GEN_DEPENDS} 3334 ${GENSCRIPTS} msp430x47176 "$(tdir_msp430x47176)" msp430all 3335 emsp430x47186.c: $(srcdir)/emulparams/msp430all.sh \ 3336 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3337 ${GEN_DEPENDS} 3338 ${GENSCRIPTS} msp430x47186 "$(tdir_msp430x47186)" msp430all 3339 emsp430x47196.c: $(srcdir)/emulparams/msp430all.sh \ 3340 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3341 ${GEN_DEPENDS} 3342 ${GENSCRIPTS} msp430x47196 "$(tdir_msp430x47196)" msp430all 3343 emsp430x47167.c: $(srcdir)/emulparams/msp430all.sh \ 3344 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3345 ${GEN_DEPENDS} 3346 ${GENSCRIPTS} msp430x47167 "$(tdir_msp430x47167)" msp430all 3347 emsp430x47177.c: $(srcdir)/emulparams/msp430all.sh \ 3348 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3349 ${GEN_DEPENDS} 3350 ${GENSCRIPTS} msp430x47177 "$(tdir_msp430x47177)" msp430all 3351 emsp430x47187.c: $(srcdir)/emulparams/msp430all.sh \ 3352 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3353 ${GEN_DEPENDS} 3354 ${GENSCRIPTS} msp430x47187 "$(tdir_msp430x47187)" msp430all 3355 emsp430x47197.c: $(srcdir)/emulparams/msp430all.sh \ 3356 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3357 ${GEN_DEPENDS} 3358 ${GENSCRIPTS} msp430x47197 "$(tdir_msp430x47197)" msp430all 3359 emsp430x5419.c: $(srcdir)/emulparams/msp430all.sh \ 3360 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3361 ${GEN_DEPENDS} 3362 ${GENSCRIPTS} msp430x5419 "$(tdir_msp430x5419)" msp430all 3363 emsp430x5435.c: $(srcdir)/emulparams/msp430all.sh \ 3364 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3365 ${GEN_DEPENDS} 3366 ${GENSCRIPTS} msp430x5435 "$(tdir_msp430x5435)" msp430all 3367 emsp430x5436.c: $(srcdir)/emulparams/msp430all.sh \ 3368 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3369 ${GEN_DEPENDS} 3370 ${GENSCRIPTS} msp430x5436 "$(tdir_msp430x5436)" msp430all 3371 emsp430x5437.c: $(srcdir)/emulparams/msp430all.sh \ 3372 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3373 ${GEN_DEPENDS} 3374 ${GENSCRIPTS} msp430x5437 "$(tdir_msp430x5437)" msp430all 3375 emsp430x5438.c: $(srcdir)/emulparams/msp430all.sh \ 3376 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3377 ${GEN_DEPENDS} 3378 ${GENSCRIPTS} msp430x5438 "$(tdir_msp430x5438)" msp430all 3379 emsp430x5510.c: $(srcdir)/emulparams/msp430all.sh \ 3380 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3381 ${GEN_DEPENDS} 3382 ${GENSCRIPTS} msp430x5510 "$(tdir_msp430x5510)" msp430all 3383 emsp430x5513.c: $(srcdir)/emulparams/msp430all.sh \ 3384 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3385 ${GEN_DEPENDS} 3386 ${GENSCRIPTS} msp430x5513 "$(tdir_msp430x5513)" msp430all 3387 emsp430x5514.c: $(srcdir)/emulparams/msp430all.sh \ 3388 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3389 ${GEN_DEPENDS} 3390 ${GENSCRIPTS} msp430x5514 "$(tdir_msp430x5514)" msp430all 3391 emsp430x5515.c: $(srcdir)/emulparams/msp430all.sh \ 3392 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3393 ${GEN_DEPENDS} 3394 ${GENSCRIPTS} msp430x5515 "$(tdir_msp430x5515)" msp430all 3395 emsp430x5517.c: $(srcdir)/emulparams/msp430all.sh \ 3396 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3397 ${GEN_DEPENDS} 3398 ${GENSCRIPTS} msp430x5517 "$(tdir_msp430x5517)" msp430all 3399 emsp430x5519.c: $(srcdir)/emulparams/msp430all.sh \ 3400 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3401 ${GEN_DEPENDS} 3402 ${GENSCRIPTS} msp430x5519 "$(tdir_msp430x5519)" msp430all 3403 emsp430x5521.c: $(srcdir)/emulparams/msp430all.sh \ 3404 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3405 ${GEN_DEPENDS} 3406 ${GENSCRIPTS} msp430x5521 "$(tdir_msp430x5521)" msp430all 3407 emsp430x5522.c: $(srcdir)/emulparams/msp430all.sh \ 3408 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3409 ${GEN_DEPENDS} 3410 ${GENSCRIPTS} msp430x5522 "$(tdir_msp430x5522)" msp430all 3411 emsp430x5524.c: $(srcdir)/emulparams/msp430all.sh \ 3412 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3413 ${GEN_DEPENDS} 3414 ${GENSCRIPTS} msp430x5524 "$(tdir_msp430x5524)" msp430all 3415 emsp430x5525.c: $(srcdir)/emulparams/msp430all.sh \ 3416 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3417 ${GEN_DEPENDS} 3418 ${GENSCRIPTS} msp430x5525 "$(tdir_msp430x5525)" msp430all 3419 emsp430x5526.c: $(srcdir)/emulparams/msp430all.sh \ 3420 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3421 ${GEN_DEPENDS} 3422 ${GENSCRIPTS} msp430x5526 "$(tdir_msp430x5526)" msp430all 3423 emsp430x5527.c: $(srcdir)/emulparams/msp430all.sh \ 3424 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3425 ${GEN_DEPENDS} 3426 ${GENSCRIPTS} msp430x5527 "$(tdir_msp430x5527)" msp430all 3427 emsp430x5528.c: $(srcdir)/emulparams/msp430all.sh \ 3428 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3429 ${GEN_DEPENDS} 3430 ${GENSCRIPTS} msp430x5528 "$(tdir_msp430x5528)" msp430all 3431 emsp430x5529.c: $(srcdir)/emulparams/msp430all.sh \ 3432 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3433 ${GEN_DEPENDS} 3434 ${GENSCRIPTS} msp430x5529 "$(tdir_msp430x5529)" msp430all 3435 emsp430x6638.c: $(srcdir)/emulparams/msp430all.sh \ 3436 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3437 ${GEN_DEPENDS} 3438 ${GENSCRIPTS} msp430x6638 "$(tdir_msp430x6638)" msp430all 3439 ecc430x5133.c: $(srcdir)/emulparams/msp430all.sh \ 3440 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3441 ${GEN_DEPENDS} 3442 ${GENSCRIPTS} cc430x5133 "$(tdir_cc430x5133)" msp430all 3443 ecc430x5125.c: $(srcdir)/emulparams/msp430all.sh \ 3444 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3445 ${GEN_DEPENDS} 3446 ${GENSCRIPTS} cc430x5125 "$(tdir_cc430x5125)" msp430all 3447 ecc430x6125.c: $(srcdir)/emulparams/msp430all.sh \ 3448 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3449 ${GEN_DEPENDS} 3450 ${GENSCRIPTS} cc430x6125 "$(tdir_cc430x6125)" msp430all 3451 ecc430x6135.c: $(srcdir)/emulparams/msp430all.sh \ 3452 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3453 ${GEN_DEPENDS} 3454 ${GENSCRIPTS} cc430x6135 "$(tdir_cc430x6135)" msp430all 3455 ecc430x6126.c: $(srcdir)/emulparams/msp430all.sh \ 3456 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3457 ${GEN_DEPENDS} 3458 ${GENSCRIPTS} cc430x6126 "$(tdir_cc430x6126)" msp430all 3459 ecc430x5137.c: $(srcdir)/emulparams/msp430all.sh \ 3460 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3461 ${GEN_DEPENDS} 3462 ${GENSCRIPTS} cc430x5137 "$(tdir_cc430x5137)" msp430all 3463 ecc430x6127.c: $(srcdir)/emulparams/msp430all.sh \ 3464 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3465 ${GEN_DEPENDS} 3466 ${GENSCRIPTS} cc430x6127 "$(tdir_cc430x6127)" msp430all 3467 ecc430x6137.c: $(srcdir)/emulparams/msp430all.sh \ 3468 $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ 3469 ${GEN_DEPENDS} 3470 ${GENSCRIPTS} cc430x6137 "$(tdir_cc430x6137)" msp430all 2956 3471 enews.c: $(srcdir)/emulparams/news.sh \ 2957 3472 $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} 2958 3473 ${GENSCRIPTS} news "$(tdir_news)" -
ld/configure.tgt
diff --git binutils-2.20.1.orig/ld/configure.tgt binutils-2.20.1/ld/configure.tgt index d6d86ab..8510b41 100644
old new mn10300-*-*) targ_emul=mn10300 426 426 mt-*elf) targ_emul=elf32mt 427 427 ;; 428 428 msp430-*-*) targ_emul=msp430x110 429 targ_extra_emuls="msp430x112 msp430x1101 msp430x1111 msp430x1121 msp430x1122 msp430x1132 msp430x122 msp430x123 msp430x1222 msp430x1232 msp430x133 msp430x135 msp430x1331 msp430x1351 msp430x147 msp430x148 msp430x149 msp430x1 55 msp430x156 msp430x157 msp430x167 msp430x168 msp430x169 msp430x1610 msp430x1611 msp430x1612 msp430x2101 msp430x2111 msp430x2121 msp430x2131 msp430x311 msp430x312 msp430x313 msp430x314 msp430x315 msp430x323 msp430x325 msp430x336 msp430x337 msp430x412 msp430x413 msp430x415 msp430x417 msp430xE423 msp430xE425 msp430xE427 msp430xW423 msp430xW425 msp430xW427 msp430xG437 msp430xG438 msp430xG439 msp430x435 msp430x436 msp430x437 msp430x447 msp430x448 msp430x449"429 targ_extra_emuls="msp430x112 msp430x1101 msp430x1111 msp430x1121 msp430x1122 msp430x1132 msp430x122 msp430x123 msp430x1222 msp430x1232 msp430x133 msp430x135 msp430x1331 msp430x1351 msp430x147 msp430x148 msp430x149 msp430x1471 msp430x1481 msp430x1491 msp430x155 msp430x156 msp430x157 msp430x167 msp430x168 msp430x169 msp430x1610 msp430x1611 msp430x1612 msp430x2001 msp430x2011 msp430x2002 msp430x2012 msp430x2003 msp430x2013 msp430x2101 msp430x2111 msp430x2112 msp430x2121 msp430x2122 msp430x2131 msp430x2101 msp430x2211 msp430x2221 msp430x2231 msp430x2232 msp430x2232 msp430x2234 msp430x2252 msp430x2254 msp430x2272 msp430x2274 msp430x233 msp430x235 msp430x2330 msp430x2350 msp430x2370 msp430x247 msp430x248 msp430x249 msp430x2410 msp430x2471 msp430x2481 msp430x2491 msp430x2416 msp430x2417 msp430x2418 msp430x2419 msp430x2616 msp430x2617 msp430x2618 msp430x2619 msp430x311 msp430x312 msp430x313 msp430x314 msp430x315 msp430x323 msp430x325 msp430x336 msp430x337 msp430x412 msp430x413 msp430x415 msp430x417 msp430x423 msp430x425 msp430x427 msp430x4250 msp430x4260 msp430x4270 msp430xE423 msp430xE425 msp430xE427 msp430xE4232 msp430xE4242 msp430xE4252 msp430xE4272 msp430xW423 msp430xW425 msp430xW427 msp430xG4250 msp430xG4260 msp430xG4270 msp430xG437 msp430xG438 msp430xG439 msp430x435 msp430x436 msp430x437 msp430x4351 msp430x4361 msp430x4371 msp430x447 msp430x448 msp430x449 msp430xG4616 msp430xG4617 msp430xG4618 msp430xG4619 msp430x4783 msp430x4784 msp430x4793 msp430x4794 msp430x47166 msp430x47176 msp430x47186 msp430x47196 msp430x47167 msp430x47177 msp430x47187 msp430x47197 msp430x5418 msp430x5419 msp430x5435 msp430x5436 msp430x5437 msp430x5438 msp430x5510 msp430x5513 msp430x5514 msp430x5515 msp430x5517 msp430x5519 msp430x5521 msp430x5522 msp430x5524 msp430x5525 msp430x5526 msp430x5527 msp430x5528 msp430x5529 msp430x6638 cc430x5133 cc430x5125 cc430x6125 cc430x6135 cc430x6126 cc430x5137 cc430x6127 cc430x6137" 430 430 ;; 431 431 ns32k-pc532-mach* | ns32k-pc532-ux*) targ_emul=pc532macha ;; 432 432 ns32k-*-netbsd* | ns32k-pc532-lites*) targ_emul=ns32knbsd -
ld/emulparams/msp430all.sh
diff --git binutils-2.20.1.orig/ld/emulparams/msp430all.sh binutils-2.20.1/ld/emulparams/msp430all.sh index 57d21c2..95b745e 100644
old new ROM_START=0xfc00 18 18 ROM_SIZE=0x3e0 19 19 RAM_START=0x0200 20 20 RAM_SIZE=128 21 STACK=0x28021 VECTORS_START=0xffe0 22 22 fi 23 23 24 24 if [ "${MSP430_NAME}" = "msp430x1101" ] ; then … … ROM_START=0xfc00 27 27 ROM_SIZE=0x3e0 28 28 RAM_START=0x0200 29 29 RAM_SIZE=128 30 STACK=0x28030 VECTORS_START=0xffe0 31 31 fi 32 32 33 33 if [ "${MSP430_NAME}" = "msp430x1111" ] ; then … … ROM_START=0xf800 36 36 ROM_SIZE=0x07e0 37 37 RAM_START=0x0200 38 38 RAM_SIZE=128 39 STACK=0x28039 VECTORS_START=0xffe0 40 40 fi 41 41 42 42 if [ "${MSP430_NAME}" = "msp430x112" ] ; then … … ROM_START=0xf000 45 45 ROM_SIZE=0xfe0 46 46 RAM_START=0x0200 47 47 RAM_SIZE=256 48 STACK=0x30048 VECTORS_START=0xffe0 49 49 fi 50 50 51 if [ "${MSP430_NAME}" = "msp430x1121" ] ; then51 if [ "${MSP430_NAME}" = "msp430x1121" -o "${MSP430_NAME}" = "msp430x1122" ] ; then 52 52 ARCH=msp:110 53 53 ROM_START=0xf000 54 54 ROM_SIZE=0x0fe0 55 55 RAM_START=0x0200 56 56 RAM_SIZE=256 57 STACK=0x300 58 fi 59 60 if [ "${MSP430_NAME}" = "msp430x1122" ] ; then 61 ARCH=msp:110 62 ROM_START=0xf000 63 ROM_SIZE=0x0fe0 64 RAM_START=0x0200 65 RAM_SIZE=256 66 STACK=0x300 57 VECTORS_START=0xffe0 67 58 fi 68 59 69 60 if [ "${MSP430_NAME}" = "msp430x1132" ] ; then … … ROM_START=0xe000 72 63 ROM_SIZE=0x1fe0 73 64 RAM_START=0x0200 74 65 RAM_SIZE=256 75 STACK=0x300 76 fi 77 78 if [ "${MSP430_NAME}" = "msp430x122" ] ; then 79 ARCH=msp:12 80 ROM_START=0xf000 81 ROM_SIZE=0xfe0 82 RAM_START=0x0200 83 RAM_SIZE=256 84 STACK=0x300 66 VECTORS_START=0xffe0 85 67 fi 86 68 87 if [ "${MSP430_NAME}" = "msp430x122 2" ] ; then69 if [ "${MSP430_NAME}" = "msp430x122" -o "${MSP430_NAME}" = "msp430x1222" ] ; then 88 70 ARCH=msp:12 89 71 ROM_START=0xf000 90 72 ROM_SIZE=0xfe0 91 73 RAM_START=0x0200 92 74 RAM_SIZE=256 93 STACK=0x30075 VECTORS_START=0xffe0 94 76 fi 95 77 96 if [ "${MSP430_NAME}" = "msp430x123" ] ; then78 if [ "${MSP430_NAME}" = "msp430x123" -o "${MSP430_NAME}" = "msp430x1232" ] ; then 97 79 ARCH=msp:12 98 80 ROM_START=0xe000 99 81 ROM_SIZE=0x1fe0 100 82 RAM_START=0x0200 101 83 RAM_SIZE=256 102 STACK=0x30084 VECTORS_START=0xffe0 103 85 fi 104 86 105 if [ "${MSP430_NAME}" = "msp430x1232" ] ; then 106 ARCH=msp:12 107 ROM_START=0xe000 108 ROM_SIZE=0x1fe0 109 RAM_START=0x0200 110 RAM_SIZE=256 111 STACK=0x300 112 fi 113 114 if [ "${MSP430_NAME}" = "msp430x133" ] ; then 87 if [ "${MSP430_NAME}" = "msp430x133" -o "${MSP430_NAME}" = "msp430x1331" ] ; then 115 88 ARCH=msp:13 116 89 ROM_START=0xe000 117 90 ROM_SIZE=0x1fe0 118 91 RAM_START=0x0200 119 92 RAM_SIZE=256 120 STACK=0x300 121 fi 122 123 if [ "${MSP430_NAME}" = "msp430x1331" ] ; then 124 ARCH=msp:13 125 ROM_START=0xe000 126 ROM_SIZE=0x1fe0 127 RAM_START=0x0200 128 RAM_SIZE=256 129 STACK=0x300 130 fi 131 132 if [ "${MSP430_NAME}" = "msp430x135" ] ; then 133 ARCH=msp:13 134 ROM_START=0xc000 135 ROM_SIZE=0x3fe0 136 RAM_START=0x0200 137 RAM_SIZE=512 138 STACK=0x400 93 VECTORS_START=0xffe0 139 94 fi 140 95 141 if [ "${MSP430_NAME}" = "msp430x135 1" ] ; then96 if [ "${MSP430_NAME}" = "msp430x135" -o "${MSP430_NAME}" = "msp430x1351" ] ; then 142 97 ARCH=msp:13 143 98 ROM_START=0xc000 144 99 ROM_SIZE=0x3fe0 145 100 RAM_START=0x0200 146 101 RAM_SIZE=512 147 STACK=0x400102 VECTORS_START=0xffe0 148 103 fi 149 104 150 if [ "${MSP430_NAME}" = "msp430x147" ] ; then105 if [ "${MSP430_NAME}" = "msp430x147" -o "${MSP430_NAME}" = "msp430x1471" ] ; then 151 106 ARCH=msp:14 152 107 ROM_START=0x8000 153 108 ROM_SIZE=0x7fe0 154 109 RAM_START=0x0200 155 RAM_SIZE=1 K156 STACK=0x600110 RAM_SIZE=1024 111 VECTORS_START=0xffe0 157 112 fi 158 113 159 if [ "${MSP430_NAME}" = "msp430x148" ] ; then114 if [ "${MSP430_NAME}" = "msp430x148" -o "${MSP430_NAME}" = "msp430x1481" ] ; then 160 115 ARCH=msp:14 161 116 ROM_START=0x4000 162 117 ROM_SIZE=0xbfe0 163 118 RAM_START=0x0200 164 RAM_SIZE= 0x0800165 STACK=0xa00119 RAM_SIZE=2048 120 VECTORS_START=0xffe0 166 121 fi 167 122 168 if [ "${MSP430_NAME}" = "msp430x149" ] ; then123 if [ "${MSP430_NAME}" = "msp430x149" -o "${MSP430_NAME}" = "msp430x1491" ] ; then 169 124 ARCH=msp:14 170 125 ROM_START=0x1100 171 126 ROM_SIZE=0xeee0 172 127 RAM_START=0x0200 173 RAM_SIZE= 0x0800174 STACK=0xa00128 RAM_SIZE=2048 129 VECTORS_START=0xffe0 175 130 fi 176 131 177 132 if [ "${MSP430_NAME}" = "msp430x155" ] ; then … … ROM_START=0xc000 180 135 ROM_SIZE=0x3fe0 181 136 RAM_START=0x0200 182 137 RAM_SIZE=512 183 STACK=0x400138 VECTORS_START=0xffe0 184 139 fi 185 140 186 141 if [ "${MSP430_NAME}" = "msp430x156" ] ; then … … ROM_START=0xa000 189 144 ROM_SIZE=0x5fe0 190 145 RAM_START=0x0200 191 146 RAM_SIZE=512 192 STACK=0x400147 VECTORS_START=0xffe0 193 148 fi 194 149 195 150 if [ "${MSP430_NAME}" = "msp430x157" ] ; then … … ARCH=msp:15 197 152 ROM_START=0x8000 198 153 ROM_SIZE=0x7fe0 199 154 RAM_START=0x0200 200 RAM_SIZE=1 K201 STACK=0x600155 RAM_SIZE=1024 156 VECTORS_START=0xffe0 202 157 fi 203 158 204 159 if [ "${MSP430_NAME}" = "msp430x167" ] ; then … … ARCH=msp:16 206 161 ROM_START=0x8000 207 162 ROM_SIZE=0x7fe0 208 163 RAM_START=0x0200 209 RAM_SIZE=1 K210 STACK=0x600164 RAM_SIZE=1024 165 VECTORS_START=0xffe0 211 166 fi 212 167 213 168 if [ "${MSP430_NAME}" = "msp430x168" ] ; then … … ARCH=msp:16 215 170 ROM_START=0x4000 216 171 ROM_SIZE=0xbfe0 217 172 RAM_START=0x0200 218 RAM_SIZE= 0x0800219 STACK=0xa00173 RAM_SIZE=2048 174 VECTORS_START=0xffe0 220 175 fi 221 176 222 177 if [ "${MSP430_NAME}" = "msp430x169" ] ; then … … ARCH=msp:16 224 179 ROM_START=0x1100 225 180 ROM_SIZE=0xeee0 226 181 RAM_START=0x0200 227 RAM_SIZE= 0x0800228 STACK=0xa00182 RAM_SIZE=2048 183 VECTORS_START=0xffe0 229 184 fi 230 185 231 186 if [ "${MSP430_NAME}" = "msp430x1610" ] ; then … … ROM_START=0x8000 234 189 ROM_SIZE=0x7fe0 235 190 RAM_START=0x1100 236 191 RAM_SIZE=0x1400 237 STACK=0x2500192 VECTORS_START=0xffe0 238 193 fi 239 194 240 195 if [ "${MSP430_NAME}" = "msp430x1611" ] ; then … … ROM_START=0x4000 243 198 ROM_SIZE=0xbfe0 244 199 RAM_START=0x1100 245 200 RAM_SIZE=0x2800 246 STACK=0x3900201 VECTORS_START=0xffe0 247 202 fi 248 203 249 204 if [ "${MSP430_NAME}" = "msp430x1612" ] ; then … … ROM_START=0x2500 252 207 ROM_SIZE=0xdae0 253 208 RAM_START=0x1100 254 209 RAM_SIZE=0x1400 255 STACK=0x2500 210 VECTORS_START=0xffe0 211 fi 212 213 if [ "${MSP430_NAME}" = "msp430x2001" -o "${MSP430_NAME}" = "msp430x2002" -o "${MSP430_NAME}" = "msp430x2003" ] ; then 214 ARCH=msp:20 215 ROM_START=0xFC00 216 ROM_SIZE=0x03e0 217 RAM_START=0x0200 218 RAM_SIZE=128 219 VECTORS_START=0xffe0 220 fi 221 222 if [ "${MSP430_NAME}" = "msp430x2011" -o "${MSP430_NAME}" = "msp430x2012" -o "${MSP430_NAME}" = "msp430x2013" ] ; then 223 ARCH=msp:20 224 ROM_START=0xF800 225 ROM_SIZE=0x07e0 226 RAM_START=0x0200 227 RAM_SIZE=128 228 VECTORS_START=0xffe0 256 229 fi 257 230 258 231 if [ "${MSP430_NAME}" = "msp430x2101" ] ; then … … ROM_START=0xFC00 261 234 ROM_SIZE=0x03e0 262 235 RAM_START=0x0200 263 236 RAM_SIZE=128 264 STACK=0x280237 VECTORS_START=0xffe0 265 238 fi 266 239 267 if [ "${MSP430_NAME}" = "msp430x2111" ] ; then240 if [ "${MSP430_NAME}" = "msp430x2111" -o "${MSP430_NAME}" = "msp430x2112" ] ; then 268 241 ARCH=msp:21 269 242 ROM_START=0xF800 270 243 ROM_SIZE=0x07e0 271 244 RAM_START=0x0200 272 245 RAM_SIZE=128 273 STACK=0x280246 VECTORS_START=0xffe0 274 247 fi 275 248 276 if [ "${MSP430_NAME}" = "msp430x2121" ] ; then249 if [ "${MSP430_NAME}" = "msp430x2121" -o "${MSP430_NAME}" = "msp430x2122" ] ; then 277 250 ARCH=msp:21 278 251 ROM_START=0xf000 279 252 ROM_SIZE=0x0fe0 280 253 RAM_START=0x0200 281 254 RAM_SIZE=256 282 STACK=0x300255 VECTORS_START=0xffe0 283 256 fi 284 257 285 if [ "${MSP430_NAME}" = "msp430x2131" ] ; then258 if [ "${MSP430_NAME}" = "msp430x2131" -o "${MSP430_NAME}" = "msp430x2132" ] ; then 286 259 ARCH=msp:21 287 260 ROM_START=0xe000 288 261 ROM_SIZE=0x1fe0 289 262 RAM_START=0x0200 290 263 RAM_SIZE=256 291 STACK=0x300 264 VECTORS_START=0xffe0 265 fi 266 267 # Warning: Value-line chips, may not be correct for other models 268 if [ "${MSP430_NAME}" = "msp430x2201" \ 269 -o "${MSP430_NAME}" = "msp430x2211" \ 270 -o "${MSP430_NAME}" = "msp430x2221" \ 271 -o "${MSP430_NAME}" = "msp430x2231" \ 272 ] ; then 273 ARCH=msp:22 274 ROM_START=0xF800 275 ROM_SIZE=0x07e0 276 RAM_START=0x0200 277 RAM_SIZE=128 278 VECTORS_START=0xffe0 279 fi 280 281 if [ "${MSP430_NAME}" = "msp430x2232" -o "${MSP430_NAME}" = "msp430x2234" ] ; then 282 ARCH=msp:22 283 ROM_START=0xe000 284 ROM_SIZE=0x1fe0 285 RAM_START=0x0200 286 RAM_SIZE=512 287 VECTORS_START=0xffe0 288 fi 289 290 if [ "${MSP430_NAME}" = "msp430x2252" -o "${MSP430_NAME}" = "msp430x2254" ] ; then 291 ARCH=msp:22 292 ROM_START=0xc000 293 ROM_SIZE=0x3fe0 294 RAM_START=0x0200 295 RAM_SIZE=512 296 VECTORS_START=0xffe0 297 fi 298 299 if [ "${MSP430_NAME}" = "msp430x2272" -o "${MSP430_NAME}" = "msp430x2274" ] ; then 300 ARCH=msp:22 301 ROM_START=0x8000 302 ROM_SIZE=0x7fe0 303 RAM_START=0x0200 304 RAM_SIZE=1024 305 VECTORS_START=0xffe0 306 fi 307 308 if [ "${MSP430_NAME}" = "msp430x233" ] ; then 309 ARCH=msp:24 310 ROM_START=0xe000 311 ROM_SIZE=0x1fe0 312 RAM_START=0x0200 313 RAM_SIZE=0x0400 314 VECTORS_START=0xffe0 315 fi 316 317 if [ "${MSP430_NAME}" = "msp430x235" ] ; then 318 ARCH=msp:24 319 ROM_START=0xc000 320 ROM_SIZE=0x3fe0 321 RAM_START=0x0200 322 RAM_SIZE=2048 323 VECTORS_START=0xffe0 324 fi 325 326 if [ "${MSP430_NAME}" = "msp430x2330" ] ; then 327 ARCH=msp:23 328 ROM_START=0xe000 329 ROM_SIZE=0x1fe0 330 RAM_START=0x0200 331 RAM_SIZE=0x0400 332 VECTORS_START=0xffe0 333 fi 334 335 if [ "${MSP430_NAME}" = "msp430x2350" ] ; then 336 ARCH=msp:23 337 ROM_START=0xc000 338 ROM_SIZE=0x3fe0 339 RAM_START=0x0200 340 RAM_SIZE=2048 341 VECTORS_START=0xffe0 342 fi 343 344 if [ "${MSP430_NAME}" = "msp430x2370" ] ; then 345 ARCH=msp:23 346 ROM_START=0x8000 347 ROM_SIZE=0x7fe0 348 RAM_START=0x0200 349 RAM_SIZE=2048 350 VECTORS_START=0xffe0 351 fi 352 353 if [ "${MSP430_NAME}" = "msp430x247" -o "${MSP430_NAME}" = "msp430x2471" ] ; then 354 ARCH=msp:24 355 ROM_START=0x8000 356 ROM_SIZE=0x7fe0 357 RAM_START=0x1100 358 RAM_SIZE=4096 359 VECTORS_START=0xffe0 360 fi 361 362 if [ "${MSP430_NAME}" = "msp430x248" -o "${MSP430_NAME}" = "msp430x2481" ] ; then 363 ARCH=msp:24 364 ROM_START=0x4000 365 ROM_SIZE=0xbfe0 366 RAM_START=0x1100 367 RAM_SIZE=4096 368 VECTORS_START=0xffe0 369 fi 370 371 if [ "${MSP430_NAME}" = "msp430x249" -o "${MSP430_NAME}" = "msp430x2491" ] ; then 372 ARCH=msp:24 373 ROM_START=0x1100 374 ROM_SIZE=0xeee0 375 RAM_START=0x0200 376 RAM_SIZE=2048 377 VECTORS_START=0xffe0 378 fi 379 380 if [ "${MSP430_NAME}" = "msp430x2410" ] ; then 381 ARCH=msp:24 382 ROM_START=0x2100 383 ROM_SIZE=0xdee0 384 RAM_START=0x1100 385 RAM_SIZE=4096 386 VECTORS_START=0xffe0 387 fi 388 389 if [ "${MSP430_NAME}" = "msp430x2416" -o "${MSP430_NAME}" = "msp430x2616" ] ; then 390 if [ "${MSP430_NAME}" = "msp430x2416" ] ; then 391 ARCH=msp:241 392 else 393 ARCH=msp:26 394 fi 395 ROM_START=0x2100 396 ROM_SIZE=0x16f00 397 INFO_START=0x1000 398 INFO_SIZE=256 399 BOOT_START=0x0c00 400 BOOT_SIZE=1024 401 RAM_START=0x1100 402 RAM_SIZE=4096 403 VECTORS_START=0xffc0 404 fi 405 406 if [ "${MSP430_NAME}" = "msp430x2417" -o "${MSP430_NAME}" = "msp430x2617" ] ; then 407 if [ "${MSP430_NAME}" = "msp430x2417" ] ; then 408 ARCH=msp:241 409 else 410 ARCH=msp:26 411 fi 412 ROM_START=0x3100 413 ROM_SIZE=0x16f00 414 INFO_START=0x1000 415 INFO_SIZE=256 416 BOOT_START=0x0c00 417 BOOT_SIZE=1024 418 RAM_START=0x1100 419 RAM_SIZE=8192 420 VECTORS_START=0xffc0 421 fi 422 423 if [ "${MSP430_NAME}" = "msp430x2418" -o "${MSP430_NAME}" = "msp430x2618" ] ; then 424 if [ "${MSP430_NAME}" = "msp430x2418" ] ; then 425 ARCH=msp:241 426 else 427 ARCH=msp:26 428 fi 429 ROM_START=0x3100 430 ROM_SIZE=0x1cf00 431 INFO_START=0x1000 432 INFO_SIZE=256 433 BOOT_START=0x0c00 434 BOOT_SIZE=1024 435 RAM_START=0x1100 436 RAM_SIZE=8192 437 VECTORS_START=0xffc0 438 fi 439 440 if [ "${MSP430_NAME}" = "msp430x2419" -o "${MSP430_NAME}" = "msp430x2619" ] ; then 441 if [ "${MSP430_NAME}" = "msp430x2419" ] ; then 442 ARCH=msp:241 443 else 444 ARCH=msp:26 445 fi 446 ROM_START=0x2100 447 ROM_SIZE=0x1df00 448 INFO_START=0x1000 449 INFO_SIZE=256 450 BOOT_START=0x0c00 451 BOOT_SIZE=1024 452 RAM_START=0x1100 453 RAM_SIZE=4096 454 VECTORS_START=0xffc0 292 455 fi 293 456 294 457 if [ "${MSP430_NAME}" = "msp430x311" ] ; then … … ROM_START=0xf800 298 461 ROM_SIZE=0x07e0 299 462 RAM_START=0x0200 300 463 RAM_SIZE=128 301 STACK=0x280464 VECTORS_START=0xffe0 302 465 fi 303 466 304 467 if [ "${MSP430_NAME}" = "msp430x312" ] ; then … … ROM_START=0xf000 308 471 ROM_SIZE=0x0fe0 309 472 RAM_START=0x0200 310 473 RAM_SIZE=256 311 STACK=0x300474 VECTORS_START=0xffe0 312 475 fi 313 476 314 477 if [ "${MSP430_NAME}" = "msp430x313" ] ; then … … ROM_START=0xe000 318 481 ROM_SIZE=0x1fe0 319 482 RAM_START=0x0200 320 483 RAM_SIZE=256 321 STACK=0x300484 VECTORS_START=0xffe0 322 485 fi 323 486 324 487 if [ "${MSP430_NAME}" = "msp430x314" ] ; then … … ROM_START=0xd000 328 491 ROM_SIZE=0x2fe0 329 492 RAM_START=0x0200 330 493 RAM_SIZE=512 331 STACK=0x400494 VECTORS_START=0xffe0 332 495 fi 333 496 334 497 if [ "${MSP430_NAME}" = "msp430x315" ] ; then … … ROM_START=0xc000 338 501 ROM_SIZE=0x3fe0 339 502 RAM_START=0x0200 340 503 RAM_SIZE=512 341 STACK=0x400504 VECTORS_START=0xffe0 342 505 fi 343 506 344 507 if [ "${MSP430_NAME}" = "msp430x323" ] ; then … … ROM_START=0xe000 348 511 ROM_SIZE=0x1fe0 349 512 RAM_START=0x0200 350 513 RAM_SIZE=256 351 STACK=0x300514 VECTORS_START=0xffe0 352 515 fi 353 516 354 517 if [ "${MSP430_NAME}" = "msp430x325" ] ; then … … ROM_START=0xc000 358 521 ROM_SIZE=0x3fe0 359 522 RAM_START=0x0200 360 523 RAM_SIZE=512 361 STACK=0x400524 VECTORS_START=0xffe0 362 525 fi 363 526 364 527 if [ "${MSP430_NAME}" = "msp430x336" ] ; then … … ROM_START=0xa000 368 531 ROM_SIZE=0x5fe0 369 532 RAM_START=0x0200 370 533 RAM_SIZE=1024 371 STACK=0x600534 VECTORS_START=0xffe0 372 535 fi 373 536 374 537 if [ "${MSP430_NAME}" = "msp430x337" ] ; then … … ROM_START=0x8000 378 541 ROM_SIZE=0x7fe0 379 542 RAM_START=0x0200 380 543 RAM_SIZE=1024 381 STACK=0x600544 VECTORS_START=0xffe0 382 545 fi 383 546 384 547 if [ "${MSP430_NAME}" = "msp430x412" ] ; then … … ROM_START=0xf000 387 550 ROM_SIZE=0x0fe0 388 551 RAM_START=0x0200 389 552 RAM_SIZE=256 390 STACK=0x300553 VECTORS_START=0xffe0 391 554 fi 392 555 393 556 if [ "${MSP430_NAME}" = "msp430x413" ] ; then … … ROM_START=0xe000 396 559 ROM_SIZE=0x1fe0 397 560 RAM_START=0x0200 398 561 RAM_SIZE=256 399 STACK=0x300562 VECTORS_START=0xffe0 400 563 fi 401 564 402 565 if [ "${MSP430_NAME}" = "msp430x415" ] ; then … … ROM_START=0xc000 405 568 ROM_SIZE=0x3fe0 406 569 RAM_START=0x0200 407 570 RAM_SIZE=512 408 STACK=0x400571 VECTORS_START=0xffe0 409 572 fi 410 573 411 574 if [ "${MSP430_NAME}" = "msp430x417" ] ; then … … ROM_START=0x8000 414 577 ROM_SIZE=0x7fe0 415 578 RAM_START=0x0200 416 579 RAM_SIZE=1024 417 STACK=0x600580 VECTORS_START=0xffe0 418 581 fi 419 582 420 if [ "${MSP430_NAME}" = "msp430x435" ] ; then 583 if [ "${MSP430_NAME}" = "msp430x423" ] ; then 584 ARCH=msp:42 585 ROM_START=0xe000 586 ROM_SIZE=0x1fe0 587 RAM_START=0x0200 588 RAM_SIZE=256 589 VECTORS_START=0xffe0 590 fi 591 592 if [ "${MSP430_NAME}" = "msp430x425" -o "${MSP430_NAME}" = "msp430x4250" ] ; then 593 ARCH=msp:42 594 ROM_START=0xc000 595 ROM_SIZE=0x3fe0 596 RAM_START=0x0200 597 if [ "${MSP430_NAME}" = "msp430x4250" ] ; then 598 RAM_SIZE=256 599 else 600 RAM_SIZE=512 601 fi 602 VECTORS_START=0xffe0 603 fi 604 605 if [ "${MSP430_NAME}" = "msp430x4260" ] ; then 606 ARCH=msp:42 607 ROM_START=0xa000 608 ROM_SIZE=0x5fe0 609 RAM_START=0x0200 610 RAM_SIZE=256 611 VECTORS_START=0xffe0 612 fi 613 614 if [ "${MSP430_NAME}" = "msp430x427" -o "${MSP430_NAME}" = "msp430x4270" ] ; then 615 ARCH=msp:42 616 ROM_START=0x8000 617 ROM_SIZE=0x7fe0 618 RAM_START=0x0200 619 if [ "${MSP430_NAME}" = "msp430x4270" ] ; then 620 RAM_SIZE=256 621 else 622 RAM_SIZE=1024 623 fi 624 VECTORS_START=0xffe0 625 fi 626 627 628 if [ "${MSP430_NAME}" = "msp430x435" -o "${MSP430_NAME}" = "msp430x4351" ] ; then 421 629 ARCH=msp:43 422 630 ROM_START=0xc000 423 631 ROM_SIZE=0x3fe0 424 632 RAM_START=0x0200 425 633 RAM_SIZE=512 426 STACK=0x400634 VECTORS_START=0xffe0 427 635 fi 428 636 429 if [ "${MSP430_NAME}" = "msp430x436" ] ; then637 if [ "${MSP430_NAME}" = "msp430x436" -o "${MSP430_NAME}" = "msp430x4361" ] ; then 430 638 ARCH=msp:43 431 639 ROM_START=0xa000 432 640 ROM_SIZE=0x5fe0 433 641 RAM_START=0x0200 434 642 RAM_SIZE=1024 435 STACK=0x600643 VECTORS_START=0xffe0 436 644 fi 437 645 438 if [ "${MSP430_NAME}" = "msp430x437" ] ; then646 if [ "${MSP430_NAME}" = "msp430x437" -o "${MSP430_NAME}" = "msp430x4371" ] ; then 439 647 ARCH=msp:43 440 648 ROM_START=0x8000 441 649 ROM_SIZE=0x7fe0 442 650 RAM_START=0x0200 443 651 RAM_SIZE=1024 444 STACK=0x600652 VECTORS_START=0xffe0 445 653 fi 446 654 447 655 if [ "${MSP430_NAME}" = "msp430x447" ] ; then … … ROM_START=0x8000 450 658 ROM_SIZE=0x7fe0 451 659 RAM_START=0x0200 452 660 RAM_SIZE=1024 453 STACK=0x600661 VECTORS_START=0xffe0 454 662 fi 455 663 456 664 if [ "${MSP430_NAME}" = "msp430x448" ] ; then … … ARCH=msp:44 458 666 ROM_START=0x4000 459 667 ROM_SIZE=0xbfe0 460 668 RAM_START=0x0200 461 RAM_SIZE= 0x0800462 STACK=0xa00669 RAM_SIZE=2048 670 VECTORS_START=0xffe0 463 671 fi 464 672 465 673 if [ "${MSP430_NAME}" = "msp430x449" ] ; then … … ARCH=msp:44 467 675 ROM_START=0x1100 468 676 ROM_SIZE=0xeee0 469 677 RAM_START=0x0200 470 RAM_SIZE= 0x0800471 STACK=0xa00678 RAM_SIZE=2048 679 VECTORS_START=0xffe0 472 680 fi 473 681 474 if [ "${MSP430_NAME}" = "msp430xE423" ] ; then 682 if [ "${MSP430_NAME}" = "msp430xE423" -o "${MSP430_NAME}" = "msp430xW423" \ 683 -o "${MSP430_NAME}" = "msp430xE4232" \ 684 ] ; then 475 685 ARCH=msp:42 476 686 ROM_START=0xe000 477 687 ROM_SIZE=0x1fe0 478 688 RAM_START=0x0200 479 689 RAM_SIZE=256 480 STACK=0x300 690 VECTORS_START=0xffe0 691 fi 692 693 if [ "${MSP430_NAME}" = "msp430xE4242" ] ; then 694 ARCH=msp:42 695 ROM_START=0xd000 696 ROM_SIZE=0x2fe0 697 RAM_START=0x0200 698 RAM_SIZE=512 699 VECTORS_START=0xffe0 481 700 fi 482 701 483 if [ "${MSP430_NAME}" = "msp430xE425" ] ; then 702 if [ "${MSP430_NAME}" = "msp430xE425" -o "${MSP430_NAME}" = "msp430xW425" \ 703 -o "${MSP430_NAME}" = "msp430xG4250" -o "${MSP430_NAME}" = "msp430xE4252" \ 704 ] ; then 484 705 ARCH=msp:42 485 706 ROM_START=0xc000 486 707 ROM_SIZE=0x3fe0 487 708 RAM_START=0x0200 709 if [ "${MSP430_NAME}" = "msp430xG4250" ] ; then 710 RAM_SIZE=256 711 else 488 712 RAM_SIZE=512 489 STACK=0x400 713 fi 714 VECTORS_START=0xffe0 490 715 fi 491 716 492 if [ "${MSP430_NAME}" = "msp430xE427" ] ; then 717 if [ "${MSP430_NAME}" = "msp430xG4260" ] ; then 718 ARCH=msp:42 719 ROM_START=0xa000 720 ROM_SIZE=0x5fe0 721 RAM_START=0x0200 722 RAM_SIZE=256 723 VECTORS_START=0xffe0 724 fi 725 726 if [ "${MSP430_NAME}" = "msp430xE427" -o "${MSP430_NAME}" = "msp430xW427" \ 727 -o "${MSP430_NAME}" = "msp430xG4270" -o "${MSP430_NAME}" = "msp430xE4272" \ 728 ] ; then 493 729 ARCH=msp:42 494 730 ROM_START=0x8000 495 731 ROM_SIZE=0x7fe0 496 732 RAM_START=0x0200 733 if [ "${MSP430_NAME}" = "msp430xG4270" ] ; then 734 RAM_SIZE=256 735 else 497 736 RAM_SIZE=1024 498 STACK=0x600 737 fi 738 VECTORS_START=0xffe0 499 739 fi 500 740 741 501 742 if [ "${MSP430_NAME}" = "msp430xG437" ] ; then 502 743 ARCH=msp:43 503 744 ROM_START=0x8000 504 745 ROM_SIZE=0x7fe0 505 746 RAM_START=0x0200 506 747 RAM_SIZE=1024 507 STACK=0x600748 VECTORS_START=0xffe0 508 749 fi 509 750 510 751 if [ "${MSP430_NAME}" = "msp430xG438" ] ; then … … ARCH=msp:43 512 753 ROM_START=0x4000 513 754 ROM_SIZE=0xbef0 514 755 RAM_START=0x0200 515 RAM_SIZE= 0x0800516 STACK=0xa00756 RAM_SIZE=2048 757 VECTORS_START=0xffe0 517 758 fi 518 759 519 760 if [ "${MSP430_NAME}" = "msp430xG439" ] ; then … … ARCH=msp:43 521 762 ROM_START=0x1100 522 763 ROM_SIZE=0xeee0 523 764 RAM_START=0x0200 524 RAM_SIZE= 0x0800525 STACK=0xa00765 RAM_SIZE=2048 766 VECTORS_START=0xffe0 526 767 fi 527 768 528 if [ "${MSP430_NAME}" = "msp430xW423" ] ; then 529 ARCH=msp:42 769 if [ "${MSP430_NAME}" = "msp430xG4616" ] ; then 770 ARCH=msp:46 771 ROM_START=0x2100 772 ROM_SIZE=0x17000 773 INFO_START=0x1000 774 INFO_SIZE=256 775 BOOT_START=0x0c00 776 BOOT_SIZE=1024 777 RAM_START=0x1100 778 RAM_SIZE=4096 779 VECTORS_START=0xffc0 780 fi 781 782 if [ "${MSP430_NAME}" = "msp430xG4617" ] ; then 783 ARCH=msp:46 784 ROM_START=0x3100 785 ROM_SIZE=0x17000 786 INFO_START=0x1000 787 INFO_SIZE=256 788 BOOT_START=0x0c00 789 BOOT_SIZE=1024 790 RAM_START=0x1100 791 RAM_SIZE=8192 792 VECTORS_START=0xffc0 793 fi 794 795 if [ "${MSP430_NAME}" = "msp430xG4618" ] ; then 796 ARCH=msp:46 797 ROM_START=0x3100 798 ROM_SIZE=0x1D000 799 INFO_START=0x1000 800 INFO_SIZE=256 801 BOOT_START=0x0c00 802 BOOT_SIZE=1024 803 RAM_START=0x1100 804 RAM_SIZE=8192 805 VECTORS_START=0xffc0 806 fi 807 808 if [ "${MSP430_NAME}" = "msp430xG4619" ] ; then 809 ARCH=msp:46 810 ROM_START=0x2100 811 ROM_SIZE=0x1E000 812 INFO_START=0x1000 813 INFO_SIZE=256 814 BOOT_START=0x0c00 815 BOOT_SIZE=1024 816 RAM_START=0x1100 817 RAM_SIZE=4096 818 VECTORS_START=0xffc0 819 fi 820 821 if [ "${MSP430_NAME}" = "msp430x4783" -o "${MSP430_NAME}" = "msp430x4784" ] ; then 822 ARCH=msp:47 823 ROM_START=0x4000 824 ROM_SIZE=0xbfe0 825 RAM_START=0x200 826 RAM_SIZE=2048 827 VECTORS_START=0xffe0 828 fi 829 830 if [ "${MSP430_NAME}" = "msp430x4793" -o "${MSP430_NAME}" = "msp430x4794" ] ; then 831 ARCH=msp:47 832 ROM_START=0x1100 833 ROM_SIZE=0xeee0 834 RAM_START=0x200 835 RAM_SIZE=2560 836 VECTORS_START=0xffe0 837 fi 838 839 if [ "${MSP430_NAME}" = "msp430x47166" -o "${MSP430_NAME}" = "msp430x47167" ] ; then 840 ARCH=msp:471 841 ROM_START=0x2100 842 ROM_SIZE=0x16f00 843 INFO_START=0x1000 844 INFO_SIZE=256 845 BOOT_START=0x0c00 846 BOOT_SIZE=1024 847 RAM_START=0x1100 848 RAM_SIZE=4096 849 VECTORS_START=0xffc0 850 fi 851 852 if [ "${MSP430_NAME}" = "msp430x47176" -o "${MSP430_NAME}" = "msp430x47177" ] ; then 853 ARCH=msp:471 854 ROM_START=0x3100 855 ROM_SIZE=0x16f00 856 INFO_START=0x1000 857 INFO_SIZE=256 858 BOOT_START=0x0c00 859 BOOT_SIZE=1024 860 RAM_START=0x1100 861 RAM_SIZE=8192 862 VECTORS_START=0xffc0 863 fi 864 865 if [ "${MSP430_NAME}" = "msp430x47186" -o "${MSP430_NAME}" = "msp430x47187" ] ; then 866 ARCH=msp:471 867 ROM_START=0x3100 868 ROM_SIZE=0x1cf00 869 INFO_START=0x1000 870 INFO_SIZE=256 871 BOOT_START=0x0c00 872 BOOT_SIZE=1024 873 RAM_START=0x1100 874 RAM_SIZE=8192 875 VECTORS_START=0xffc0 876 fi 877 878 if [ "${MSP430_NAME}" = "msp430x47196" -o "${MSP430_NAME}" = "msp430x47197" ] ; then 879 ARCH=msp:471 880 ROM_START=0x2100 881 ROM_SIZE=0x1df00 882 INFO_START=0x1000 883 INFO_SIZE=256 884 BOOT_START=0x0c00 885 BOOT_SIZE=1024 886 RAM_START=0x1100 887 RAM_SIZE=4096 888 VECTORS_START=0xffc0 889 fi 890 891 if [ "${MSP430_NAME}" = "msp430x5418" -o "${MSP430_NAME}" = "msp430x5419" ] ; then 892 ARCH=msp:54 893 ROM_START=0x5c00 894 ROM_SIZE=0x20000 895 INFO_START=0x1800 896 INFO_SIZE=512 897 BOOT_START=0x1000 898 BOOT_SIZE=2048 899 RAM_START=0x1c00 900 RAM_SIZE=16384 901 VECTORS_START=0xff80 902 fi 903 904 if [ "${MSP430_NAME}" = "msp430x5435" -o "${MSP430_NAME}" = "msp430x5436" ] ; then 905 ARCH=msp:54 906 ROM_START=0x5c00 907 ROM_SIZE=0x30000 908 INFO_START=0x1800 909 INFO_SIZE=512 910 BOOT_START=0x1000 911 BOOT_SIZE=2048 912 RAM_START=0x1c00 913 RAM_SIZE=16384 914 VECTORS_START=0xff80 915 fi 916 917 if [ "${MSP430_NAME}" = "msp430x5437" -o "${MSP430_NAME}" = "msp430x5438" ] ; then 918 ARCH=msp:54 919 ROM_START=0x5c00 920 ROM_SIZE=0x40000 921 INFO_START=0x1800 922 INFO_SIZE=512 923 BOOT_START=0x1000 924 BOOT_SIZE=2048 925 RAM_START=0x1c00 926 RAM_SIZE=16384 927 VECTORS_START=0xff80 928 fi 929 930 if [ "${MSP430_NAME}" = "cc430x5133" ] ; then 931 ARCH=msp:54 530 932 ROM_START=0xe000 531 ROM_SIZE=0x1fe0 532 RAM_START=0x0200 533 RAM_SIZE=256 534 STACK=0x300 933 ROM_SIZE=0x2000 934 INFO_START=0x1800 935 INFO_SIZE=512 936 BOOT_START=0x1000 937 BOOT_SIZE=2048 938 RAM_START=0x1c00 939 RAM_SIZE=2048 940 VECTORS_START=0xff80 535 941 fi 536 942 537 if [ "${MSP430_NAME}" = " msp430xW425" ] ; then538 ARCH=msp: 42943 if [ "${MSP430_NAME}" = "cc430x5125" -o "${MSP430_NAME}" = "cc430x6125" -o "${MSP430_NAME}" = "cc430x6135" ] ; then 944 ARCH=msp:54 539 945 ROM_START=0xc000 540 ROM_SIZE=0x3fe0 541 RAM_START=0x0200 542 RAM_SIZE=512 543 STACK=0x400 946 ROM_SIZE=0x4000 947 INFO_START=0x1800 948 INFO_SIZE=512 949 BOOT_START=0x1000 950 BOOT_SIZE=2048 951 RAM_START=0x1c00 952 RAM_SIZE=2048 953 VECTORS_START=0xff80 544 954 fi 545 955 546 if [ "${MSP430_NAME}" = " msp430xW427" ] ; then547 ARCH=msp: 42956 if [ "${MSP430_NAME}" = "cc430x6126" ] ; then 957 ARCH=msp:54 548 958 ROM_START=0x8000 549 ROM_SIZE=0x7fe0 550 RAM_START=0x0200 551 RAM_SIZE=0x400 552 STACK=0x600 959 ROM_SIZE=0x8000 960 INFO_START=0x1800 961 INFO_SIZE=512 962 BOOT_START=0x1000 963 BOOT_SIZE=2048 964 RAM_START=0x1c00 965 RAM_SIZE=2048 966 VECTORS_START=0xff80 967 fi 968 969 if [ "${MSP430_NAME}" = "cc430x5137" -o "${MSP430_NAME}" = "cc430x6127" -o "${MSP430_NAME}" = "cc430x6137" ] ; then 970 ARCH=msp:54 971 ROM_START=0x8000 972 ROM_SIZE=0x8000 973 INFO_START=0x1800 974 INFO_SIZE=512 975 BOOT_START=0x1000 976 BOOT_SIZE=2048 977 RAM_START=0x1c00 978 RAM_SIZE=4096 979 VECTORS_START=0xff80 980 fi 981 982 if [ "${MSP430_NAME}" = "msp430x5510" ] ; then 983 ARCH=msp:54 984 ROM_START=0x8000 985 ROM_SIZE=0x8001 986 INFO_START=0x1800 987 INFO_SIZE=512 988 BOOT_START=0x1000 989 BOOT_SIZE=2048 990 RAM_START=0x2400 991 RAM_SIZE=4096 992 VECTORS_START=0xff80 993 fi 994 995 if [ "${MSP430_NAME}" = "msp430x5513" ] ; then 996 ARCH=msp:54 997 ROM_START=0x8000 998 ROM_SIZE=0x8001 999 INFO_START=0x1800 1000 INFO_SIZE=512 1001 BOOT_START=0x1000 1002 BOOT_SIZE=2048 1003 RAM_START=0x2400 1004 RAM_SIZE=4096 1005 VECTORS_START=0xff80 1006 fi 1007 1008 if [ "${MSP430_NAME}" = "msp430x5514" ] ; then 1009 ARCH=msp:54 1010 ROM_START=0x4400 1011 ROM_SIZE=0x10000 1012 INFO_START=0x1800 1013 INFO_SIZE=512 1014 BOOT_START=0x1000 1015 BOOT_SIZE=2048 1016 RAM_START=0x2400 1017 RAM_SIZE=4096 1018 VECTORS_START=0xff80 1019 fi 1020 1021 if [ "${MSP430_NAME}" = "msp430x5515" ] ; then 1022 ARCH=msp:54 1023 ROM_START=0x4400 1024 ROM_SIZE=0x10000 1025 INFO_START=0x1800 1026 INFO_SIZE=512 1027 BOOT_START=0x1000 1028 BOOT_SIZE=2048 1029 RAM_START=0x2400 1030 RAM_SIZE=4096 1031 VECTORS_START=0xff80 1032 fi 1033 1034 if [ "${MSP430_NAME}" = "msp430x5517" ] ; then 1035 ARCH=msp:54 1036 ROM_START=0x4400 1037 ROM_SIZE=0x18000 1038 INFO_START=0x1800 1039 INFO_SIZE=512 1040 BOOT_START=0x1000 1041 BOOT_SIZE=2048 1042 RAM_START=0x2400 1043 RAM_SIZE=6144 1044 VECTORS_START=0xff80 1045 fi 1046 1047 if [ "${MSP430_NAME}" = "msp430x5519" ] ; then 1048 ARCH=msp:54 1049 ROM_START=0x4400 1050 ROM_SIZE=0x20000 1051 INFO_START=0x1800 1052 INFO_SIZE=512 1053 BOOT_START=0x1000 1054 BOOT_SIZE=2048 1055 RAM_START=0x2400 1056 RAM_SIZE=8192 1057 VECTORS_START=0xff80 1058 fi 1059 1060 if [ "${MSP430_NAME}" = "msp430x5521" ] ; then 1061 ARCH=msp:54 1062 ROM_START=0x8000 1063 ROM_SIZE=0x8001 1064 INFO_START=0x1800 1065 INFO_SIZE=512 1066 BOOT_START=0x1000 1067 BOOT_SIZE=2048 1068 RAM_START=0x2400 1069 RAM_SIZE=6144 1070 VECTORS_START=0xff80 1071 fi 1072 1073 if [ "${MSP430_NAME}" = "msp430x5522" ] ; then 1074 ARCH=msp:54 1075 ROM_START=0x8000 1076 ROM_SIZE=0x8001 1077 INFO_START=0x1800 1078 INFO_SIZE=512 1079 BOOT_START=0x1000 1080 BOOT_SIZE=2048 1081 RAM_START=0x2400 1082 RAM_SIZE=8192 1083 VECTORS_START=0xff80 1084 fi 1085 1086 if [ "${MSP430_NAME}" = "msp430x5524" ] ; then 1087 ARCH=msp:54 1088 ROM_START=0x4400 1089 ROM_SIZE=0x10000 1090 INFO_START=0x1800 1091 INFO_SIZE=512 1092 BOOT_START=0x1000 1093 BOOT_SIZE=2048 1094 RAM_START=0x2400 1095 RAM_SIZE=4096 1096 VECTORS_START=0xff80 1097 fi 1098 1099 if [ "${MSP430_NAME}" = "msp430x5525" ] ; then 1100 ARCH=msp:54 1101 ROM_START=0x4400 1102 ROM_SIZE=0x10000 1103 INFO_START=0x1800 1104 INFO_SIZE=512 1105 BOOT_START=0x1000 1106 BOOT_SIZE=2048 1107 RAM_START=0x2400 1108 RAM_SIZE=4096 1109 VECTORS_START=0xff80 1110 fi 1111 1112 if [ "${MSP430_NAME}" = "msp430x5526" ] ; then 1113 ARCH=msp:54 1114 ROM_START=0x4400 1115 ROM_SIZE=0x18000 1116 INFO_START=0x1800 1117 INFO_SIZE=512 1118 BOOT_START=0x1000 1119 BOOT_SIZE=2048 1120 RAM_START=0x2400 1121 RAM_SIZE=6144 1122 VECTORS_START=0xff80 1123 fi 1124 1125 if [ "${MSP430_NAME}" = "msp430x5527" ] ; then 1126 ARCH=msp:54 1127 ROM_START=0x4400 1128 ROM_SIZE=0x18000 1129 INFO_START=0x1800 1130 INFO_SIZE=512 1131 BOOT_START=0x1000 1132 BOOT_SIZE=2048 1133 RAM_START=0x2400 1134 RAM_SIZE=6144 1135 VECTORS_START=0xff80 553 1136 fi 1137 1138 if [ "${MSP430_NAME}" = "msp430x5528" ] ; then 1139 ARCH=msp:54 1140 ROM_START=0x4400 1141 ROM_SIZE=0x20000 1142 INFO_START=0x1800 1143 INFO_SIZE=512 1144 BOOT_START=0x1000 1145 BOOT_SIZE=2048 1146 RAM_START=0x2400 1147 RAM_SIZE=8192 1148 VECTORS_START=0xff80 1149 fi 1150 1151 if [ "${MSP430_NAME}" = "msp430x5529" ] ; then 1152 ARCH=msp:54 1153 ROM_START=0x4400 1154 ROM_SIZE=0x20000 1155 INFO_START=0x1800 1156 INFO_SIZE=512 1157 BOOT_START=0x1000 1158 BOOT_SIZE=2048 1159 RAM_START=0x2400 1160 RAM_SIZE=8192 1161 VECTORS_START=0xff80 1162 fi 1163 1164 if [ "${MSP430_NAME}" = "msp430x6638" ] ; then 1165 ARCH=msp:54 1166 ROM_START=0x8000 1167 ROM_SIZE=0x40000 1168 INFO_START=0x1800 1169 INFO_SIZE=512 1170 BOOT_START=0x1000 1171 BOOT_SIZE=2048 1172 RAM_START=0x2400 1173 RAM_SIZE=16384 1174 VECTORS_START=0xff80 1175 fi 1176 1177 STACK=$(printf "0x%x" $(( RAM_START + RAM_SIZE )) ) 1178 VECTORS_SIZE=$((0x10000 - VECTORS_START)) -
ld/scripttempl/elf32msp430.sc
diff --git binutils-2.20.1.orig/ld/scripttempl/elf32msp430.sc binutils-2.20.1/ld/scripttempl/elf32msp430.sc index cbffe48..825640d 100644
old new HEAP_SECTION_MSP430=".heap ${RELOCATING-0} : 14 14 ${RELOCATING+ PROVIDE (__heap_bottom = .) ; } 15 15 ${RELOCATING+ PROVIDE (__heap_top = ${HEAP_START} + ${HEAP_LENGTH}) ; } 16 16 } ${RELOCATING+ > heap}" 17 HEAP_MEMORY_MSP430="heap(rwx) : ORIGIN = $HEAP_START,LENGTH = $HEAP_LENGTH"17 HEAP_MEMORY_MSP430="heap(rwx) : ORIGIN = $HEAP_START, LENGTH = $HEAP_LENGTH" 18 18 fi 19 19 20 ROM_END=$(( $ROM_START + $ROM_SIZE )) 21 if [ $ROM_END -gt 65536 ] 22 then 23 NEAR_ROM_SIZE=$(printf "0x%x" $(( $VECTORS_START - $ROM_START )) ) 24 FAR_ROM_SIZE=$(printf "0x%x" $(( $ROM_START + $ROM_SIZE - 0x10000 )) ) 25 26 TEXT_REGION_MSP430="text (rx) : ORIGIN = $ROM_START, LENGTH = $NEAR_ROM_SIZE 27 fartext(rx) : ORIGIN = 0x10000, LENGTH = $FAR_ROM_SIZE" 28 29 FARTEXT_SECTION_MSP430="/* Extended address space, accessed with extended instructions. */ 30 .fartext : 31 { 32 ${RELOCATING+. = ALIGN(2);} 33 *(.fartext) 34 ${RELOCATING+. = ALIGN(2);} 35 *(.fartext.*) 36 37 _efartext = .; 38 } ${RELOCATING+ > fartext}" 39 else 40 TEXT_REGION_MSP430="text (rx) : ORIGIN = $ROM_START, LENGTH = $ROM_SIZE" 41 FARTEXT_SECTION_MSP430="" 42 fi 20 43 21 44 cat <<EOF 22 45 OUTPUT_FORMAT("${OUTPUT_FORMAT}","${OUTPUT_FORMAT}","${OUTPUT_FORMAT}") … … OUTPUT_ARCH(${ARCH}) 24 47 25 48 MEMORY 26 49 { 27 text (rx) : ORIGIN = $ROM_START, LENGTH = $ROM_SIZE28 data (rwx) : ORIGIN = $RAM_START,LENGTH = $RAM_SIZE29 vectors (rw) : ORIGIN = 0xffe0, LENGTH = 0x2030 bootloader(rx) : ORIGIN = 0x0c00, LENGTH = 1K31 infomem(rx) : ORIGIN = 0x1000, LENGTH = 25632 infomemnobits(rx) : ORIGIN = 0x1000, LENGTH = 25650 ${TEXT_REGION_MSP430} 51 data (rwx) : ORIGIN = $RAM_START, LENGTH = $RAM_SIZE 52 vectors (rw) : ORIGIN = $VECTORS_START, LENGTH = $VECTORS_SIZE 53 bootloader(rx) : ORIGIN = ${BOOT_START-0x0c00}, LENGTH = ${BOOT_SIZE-1K} 54 infomem(rx) : ORIGIN = ${INFO_START-0x1000}, LENGTH = ${INFO_SIZE-256} 55 infomemnobits(rx) : ORIGIN = ${INFO_START-0x1000}, LENGTH = ${INFO_SIZE-256} 33 56 ${HEAP_MEMORY_MSP430} 34 57 } 35 58 … … SECTIONS 100 123 { 101 124 ${RELOCATING+. = ALIGN(2);} 102 125 *(.init) 103 *(.init0) /* Start here after reset. */ 104 *(.init1) 105 *(.init2) /* Copy data loop */ 106 *(.init3) 107 *(.init4) /* Clear bss */ 108 *(.init5) 109 *(.init6) /* C++ constructors. */ 110 *(.init7) 111 *(.init8) 112 *(.init9) /* Call main(). */ 126 KEEP(*(.init)) 127 *(.init0) /* Start here after reset. */ 128 KEEP(*(.init0)) 129 *(.init1) /* User definable. */ 130 KEEP(*(.init1)) 131 *(.init2) /* Initialize stack. */ 132 KEEP(*(.init2)) 133 *(.init3) /* Initialize hardware, user definable. */ 134 KEEP(*(.init3)) 135 *(.init4) /* Copy data to .data, clear bss. */ 136 KEEP(*(.init4)) 137 *(.init5) /* User definable. */ 138 KEEP(*(.init5)) 139 *(.init6) /* C++ constructors. */ 140 KEEP(*(.init6)) 141 *(.init7) /* User definable. */ 142 KEEP(*(.init7)) 143 *(.init8) /* User definable. */ 144 KEEP(*(.init8)) 145 *(.init9) /* Call main(). */ 146 KEEP(*(.init9)) 113 147 114 148 ${CONSTRUCTING+ __ctors_start = . ; } 115 149 ${CONSTRUCTING+ *(.ctors) } 150 ${CONSTRUCTING+ KEEP(*(.ctors)) } 116 151 ${CONSTRUCTING+ __ctors_end = . ; } 117 152 ${CONSTRUCTING+ __dtors_start = . ; } 118 153 ${CONSTRUCTING+ *(.dtors) } 154 ${CONSTRUCTING+ KEEP(*(.dtors)) } 119 155 ${CONSTRUCTING+ __dtors_end = . ; } 120 156 121 157 ${RELOCATING+. = ALIGN(2);} … … SECTIONS 124 160 *(.text.*) 125 161 126 162 ${RELOCATING+. = ALIGN(2);} 127 *(.fini9) /* */ 128 *(.fini8) 129 *(.fini7) 130 *(.fini6) /* C++ destructors. */ 131 *(.fini5) 132 *(.fini4) 133 *(.fini3) 134 *(.fini2) 135 *(.fini1) 163 *(.fini9) /* Jumps here after main(). User definable. */ 164 KEEP(*(.fini9)) 165 *(.fini8) /* User definable. */ 166 KEEP(*(.fini8)) 167 *(.fini7) /* User definable. */ 168 KEEP(*(.fini7)) 169 *(.fini6) /* C++ destructors. */ 170 KEEP(*(.fini6)) 171 *(.fini5) /* User definable. */ 172 KEEP(*(.fini5)) 173 *(.fini4) /* User definable. */ 174 KEEP(*(.fini4)) 175 *(.fini3) /* User definable. */ 176 KEEP(*(.fini3)) 177 *(.fini2) /* User definable. */ 178 KEEP(*(.fini2)) 179 *(.fini1) /* User definable. */ 180 KEEP(*(.fini1)) 136 181 *(.fini0) /* Infinite loop after program termination. */ 182 KEEP(*(.fini0)) 137 183 *(.fini) 184 KEEP(*(.fini)) 138 185 139 186 _etext = .; 140 187 } ${RELOCATING+ > text} 141 188 142 .data ${RELOCATING-0} : ${RELOCATING+AT (ADDR (.text) + SIZEOF (.text))}189 .data ${RELOCATING-0} : 143 190 { 144 191 ${RELOCATING+ PROVIDE (__data_start = .) ; } 145 192 ${RELOCATING+. = ALIGN(2);} 146 193 *(.data) 194 *(SORT_BY_ALIGNMENT(.data.*)) 147 195 ${RELOCATING+. = ALIGN(2);} 148 196 *(.gnu.linkonce.d*) 149 197 ${RELOCATING+. = ALIGN(2);} 150 198 ${RELOCATING+ _edata = . ; } 151 } ${RELOCATING+ > data} 199 } ${RELOCATING+ > data AT > text} 200 ${RELOCATING+ PROVIDE (__data_load_start = LOADADDR(.data) ); } 201 ${RELOCATING+ PROVIDE (__data_size = SIZEOF(.data) ); } 152 202 153 203 /* Bootloader. */ 154 204 .bootloader ${RELOCATING-0} : … … SECTIONS 175 225 *(.infomemnobits.*) 176 226 } ${RELOCATING+ > infomemnobits} 177 227 178 .bss ${RELOCATING + SIZEOF(.data) + ADDR(.data)} :228 .bss ${RELOCATING-0} : 179 229 { 180 230 ${RELOCATING+ PROVIDE (__bss_start = .) ; } 181 231 *(.bss) 232 *(SORT_BY_ALIGNMENT(.bss.*)) 182 233 *(COMMON) 183 234 ${RELOCATING+ PROVIDE (__bss_end = .) ; } 184 235 ${RELOCATING+ _end = . ; } 185 236 } ${RELOCATING+ > data} 237 ${RELOCATING+ PROVIDE (__bss_size = SIZEOF(.bss) ); } 186 238 187 .noinit ${RELOCATING + SIZEOF(.bss) + ADDR(.bss)} :239 .noinit ${RELOCATING-0} : 188 240 { 189 241 ${RELOCATING+ PROVIDE (__noinit_start = .) ; } 190 242 *(.noinit) 243 *(.noinit.*) 191 244 *(COMMON) 192 245 ${RELOCATING+ PROVIDE (__noinit_end = .) ; } 193 246 ${RELOCATING+ _end = . ; } … … SECTIONS 197 250 { 198 251 ${RELOCATING+ PROVIDE (__vectors_start = .) ; } 199 252 *(.vectors*) 253 KEEP(*(.vectors*)) 200 254 ${RELOCATING+ _vectors_end = . ; } 201 255 } ${RELOCATING+ > vectors} 202 256 257 ${FARTEXT_SECTION_MSP430} 203 258 ${HEAP_SECTION_MSP430} 204 259 205 260 /* Stabs for profiling information*/ … … SECTIONS 239 294 .debug_loc 0 : { *(.debug_loc) } 240 295 .debug_macinfo 0 : { *(.debug_macinfo) } 241 296 297 /* DWARF 3 */ 298 .debug_pubtypes 0 : { *(.debug_pubtypes) } 299 .debug_ranges 0 : { *(.debug_ranges) } 300 242 301 PROVIDE (__stack = ${STACK}) ; 243 302 PROVIDE (__data_start_rom = _etext) ; 244 303 PROVIDE (__data_end_rom = _etext + SIZEOF (.data)) ; -
ld/scripttempl/elf32msp430_3.sc
diff --git binutils-2.20.1.orig/ld/scripttempl/elf32msp430_3.sc binutils-2.20.1/ld/scripttempl/elf32msp430_3.sc index 15eb517..7b7d0fb 100644
old new OUTPUT_ARCH(${ARCH}) 4 4 5 5 MEMORY 6 6 { 7 text (rx) : ORIGIN = $ROM_START, LENGTH = $ROM_SIZE8 data (rwx) : ORIGIN = $RAM_START, LENGTH = $RAM_SIZE9 vectors (rw) : ORIGIN = 0xffe0, LENGTH = 0x207 text (rx) : ORIGIN = $ROM_START, LENGTH = $ROM_SIZE 8 data (rwx) : ORIGIN = $RAM_START, LENGTH = $RAM_SIZE 9 vectors (rw) : ORIGIN = $VECTORS_START, LENGTH = $VECTORS_SIZE 10 10 } 11 11 12 12 SECTIONS … … SECTIONS 76 76 { 77 77 ${RELOCATING+. = ALIGN(2);} 78 78 *(.init) 79 *(.init0) /* Start here after reset. */ 80 *(.init1) 81 *(.init2) 82 *(.init3) 83 *(.init4) 84 *(.init5) 85 *(.init6) /* C++ constructors. */ 86 *(.init7) 87 *(.init8) 88 *(.init9) /* Call main(). */ 79 KEEP(*(.init)) 80 *(.init0) /* Start here after reset. */ 81 KEEP(*(.init0)) 82 *(.init1) /* User definable. */ 83 KEEP(*(.init1)) 84 *(.init2) /* Initialize stack. */ 85 KEEP(*(.init2)) 86 *(.init3) /* Initialize hardware, user definable. */ 87 KEEP(*(.init3)) 88 *(.init4) /* Copy data to .data, clear bss. */ 89 KEEP(*(.init4)) 90 *(.init5) /* User definable. */ 91 KEEP(*(.init5)) 92 *(.init6) /* C++ constructors. */ 93 KEEP(*(.init6)) 94 *(.init7) /* User definable. */ 95 KEEP(*(.init7)) 96 *(.init8) /* User definable. */ 97 KEEP(*(.init8)) 98 *(.init9) /* Call main(). */ 99 KEEP(*(.init9)) 89 100 90 101 ${CONSTRUCTING+ __ctors_start = . ; } 91 102 ${CONSTRUCTING+ *(.ctors) } 103 ${CONSTRUCTING+ KEEP(*(.ctors)) } 92 104 ${CONSTRUCTING+ __ctors_end = . ; } 93 105 ${CONSTRUCTING+ __dtors_start = . ; } 94 106 ${CONSTRUCTING+ *(.dtors) } 107 ${CONSTRUCTING+ KEEP(*(.dtors)) } 95 108 ${CONSTRUCTING+ __dtors_end = . ; } 96 109 97 110 ${RELOCATING+. = ALIGN(2);} … … SECTIONS 100 113 *(.text.*) 101 114 102 115 ${RELOCATING+. = ALIGN(2);} 103 *(.fini9) 104 *(.fini8) 105 *(.fini7) 106 *(.fini6) /* C++ destructors. */ 107 *(.fini5) 108 *(.fini4) 109 *(.fini3) 110 *(.fini2) 111 *(.fini1) 116 *(.fini9) /* Jumps here after main(). User definable. */ 117 KEEP(*(.fini9)) 118 *(.fini8) /* User definable. */ 119 KEEP(*(.fini8)) 120 *(.fini7) /* User definable. */ 121 KEEP(*(.fini7)) 122 *(.fini6) /* C++ destructors. */ 123 KEEP(*(.fini6)) 124 *(.fini5) /* User definable. */ 125 KEEP(*(.fini5)) 126 *(.fini4) /* User definable. */ 127 KEEP(*(.fini4)) 128 *(.fini3) /* User definable. */ 129 KEEP(*(.fini3)) 130 *(.fini2) /* User definable. */ 131 KEEP(*(.fini2)) 132 *(.fini1) /* User definable. */ 133 KEEP(*(.fini1)) 112 134 *(.fini0) /* Infinite loop after program termination. */ 135 KEEP(*(.fini0)) 113 136 *(.fini) 137 KEEP(*(.fini)) 114 138 115 139 ${RELOCATING+ _etext = . ; } 116 140 } ${RELOCATING+ > text} 117 141 118 .data ${RELOCATING-0} : ${RELOCATING+AT (ADDR (.text) + SIZEOF (.text))}142 .data ${RELOCATING-0} : 119 143 { 120 144 ${RELOCATING+ PROVIDE (__data_start = .) ; } 121 145 *(.data) 146 *(SORT_BY_ALIGNMENT(.data.*)) 122 147 *(.gnu.linkonce.d*) 123 148 ${RELOCATING+. = ALIGN(2);} 124 149 ${RELOCATING+ _edata = . ; } 125 } ${RELOCATING+ > data} 150 } ${RELOCATING+ > data AT > text} 151 ${RELOCATING+ PROVIDE (__data_load_start = LOADADDR(.data) ); } 152 ${RELOCATING+ PROVIDE (__data_size = SIZEOF(.data) ); } 126 153 127 .bss ${RELOCATING + SIZEOF(.data) + ADDR(.data)} :154 .bss ${RELOCATING-0} : 128 155 { 129 156 ${RELOCATING+ PROVIDE (__bss_start = .) ; } 130 157 *(.bss) 158 *(SORT_BY_ALIGNMENT(.bss.*)) 131 159 *(COMMON) 132 160 ${RELOCATING+ PROVIDE (__bss_end = .) ; } 133 161 ${RELOCATING+ _end = . ; } 134 162 } ${RELOCATING+ > data} 163 ${RELOCATING+ PROVIDE (__bss_size = SIZEOF(.bss) ); } 135 164 136 .noinit ${RELOCATING + SIZEOF(.bss) + ADDR(.bss)} :165 .noinit ${RELOCATING-0} : 137 166 { 138 167 ${RELOCATING+ PROVIDE (__noinit_start = .) ; } 139 168 *(.noinit) 169 *(SORT_BY_ALIGNMENT(.noinit.*)) 140 170 *(COMMON) 141 171 ${RELOCATING+ PROVIDE (__noinit_end = .) ; } 142 172 ${RELOCATING+ _end = . ; } … … SECTIONS 146 176 { 147 177 ${RELOCATING+ PROVIDE (__vectors_start = .) ; } 148 178 *(.vectors*) 179 KEEP(*(.vectors*)) 149 180 ${RELOCATING+ _vectors_end = . ; } 150 181 } ${RELOCATING+ > vectors} 151 182 -
opcodes/msp430-dis.c
diff --git binutils-2.20.1.orig/opcodes/msp430-dis.c binutils-2.20.1/opcodes/msp430-dis.c index c4a86eb..623fa79 100644
old new msp430dis_opcode (bfd_vma addr, disassemble_info *info) 51 51 return bfd_getl16 (buffer); 52 52 } 53 53 54 static unsigned short 55 msp430dis_operand (bfd_vma addr, disassemble_info *info, int reg, int am, int *cmd_len) 56 { 57 static int const op_length [][5] = 58 { 59 // am | reg 0 1 2 3 >3 60 /* 0 */ { 0, 0, 0, 0, 0 }, // Rn 61 /* 1 */ { 2, 2, 2, 0, 2 }, // x(Rn) 62 /* 2 */ { 0, 0, 0, 0, 0 }, // @Rn 63 /* 3 */ { 2, 0, 0, 0, 0 }, // @Rn+ 64 }; 65 if (reg >= (int)(sizeof(op_length[0]) / sizeof(op_length[0][0]))) 66 reg = sizeof(op_length[0]) / sizeof(op_length[0][0])- 1; 67 68 if (op_length[am][reg]) 69 { 70 bfd_byte buffer[2]; 71 int status = info->read_memory_func (addr, buffer, 2, info); 72 if (status != 0) 73 { 74 info->memory_error_func (status, addr, info); 75 return -1; 76 } 77 *cmd_len += 2; 78 return bfd_getl16 (buffer); 79 } 80 return 0; 81 } 82 83 typedef enum 84 { 85 OP_20BIT, 86 OP_16BIT, 87 OP_20BIT_HEX, 88 OP_16BIT_HEX, 89 OP_DECIMAL, 90 } operand_t; 91 92 static void 93 msp430x_decode_operand(int reg, int am, int addr, int dst, operand_t size, char *op, char *comm) 94 { 95 if (op) // if operand not hidden in emulated instruction 96 switch (am) 97 { 98 case 0: // Rn 99 if (reg == 3) 100 { 101 sprintf (op, "#0"); // constant #0 102 sprintf (comm, "r3 As==00"); 103 } 104 else 105 { 106 sprintf (op, "r%d", reg); 107 } 108 break; 109 case 1: // x(Rn) 110 if (reg == 0) // Symbolic, ADDR 111 { 112 if (size == OP_20BIT || size == OP_20BIT_HEX) 113 sprintf (op, "0x%05x", dst & 0xfffff); 114 else 115 sprintf (op, "0x%04x", dst & 0xffff); 116 sprintf (comm, "PC rel. 0x%05x", ((int)addr + dst) & 0xfffff); 117 } 118 else if (reg == 2) // Absolute, &ADDR 119 { 120 if (size == OP_20BIT || size == OP_20BIT_HEX) 121 sprintf (op, "&0x%05x", dst & 0xfffff); 122 else 123 sprintf (op, "&0x%04x", dst & 0xffff); 124 } 125 else if (reg == 3) // constant #1 126 { 127 sprintf (op, "#1"); 128 sprintf (comm, "r3 As==01"); 129 } 130 else // Indexed, x(Rn) 131 { 132 sprintf (op, "%d(r%d)", dst, reg); 133 if (size == OP_20BIT || size == OP_20BIT_HEX) 134 sprintf (comm, "0x%05x(r%d)", dst & 0xfffff, reg); 135 else 136 sprintf (comm, "0x%04x(r%d)", dst & 0xffff, reg); 137 } 138 break; 139 case 2: // @Rn 140 if (reg == 2) // constant #4 141 { 142 sprintf (op, "#4"); 143 sprintf (comm, "r2 As==10"); 144 } 145 else if(reg == 3) // constant #2 146 { 147 sprintf (op, "#2"); 148 sprintf (comm, "r3 As==10"); 149 } 150 else 151 { 152 sprintf (op, "@r%d", reg); 153 } 154 break; 155 case 3: // @Rn+ 156 switch (reg) 157 { 158 case 0: // immediate, #N 159 switch (size) 160 { 161 case OP_16BIT: 162 sprintf (op, "#%d", dst); 163 sprintf (comm, "#0x%04x", dst & 0xffff); 164 break; 165 case OP_16BIT_HEX: 166 sprintf (op, "#0x%04x", dst & 0xffff); 167 break; 168 case OP_20BIT: 169 sprintf (op, "#%d", dst); 170 sprintf (comm, "#0x%05x", dst & 0xfffff); 171 break; 172 case OP_20BIT_HEX: 173 sprintf (op, "#0x%05x", dst & 0xfffff); 174 break; 175 default: // #n in rxxm 176 sprintf (op, "#%d", dst); 177 break; 178 } 179 break; 180 case 2: // constant #8 181 sprintf (op, "#8"); 182 sprintf (comm, "r2 As==11"); 183 break; 184 case 3: // constant #-1 185 sprintf (op, "#-1"); 186 sprintf (comm, "r3 As==11"); 187 break; 188 default: 189 sprintf (op, "@r%d+", reg); 190 break; 191 } 192 break; 193 } 194 } 195 54 196 static int 55 msp430_nooperands (struct msp430_opcode_s *opcode,197 msp430_nooperands (struct msp430_opcode_s const *opcode, 56 198 bfd_vma addr ATTRIBUTE_UNUSED, 57 199 unsigned short insn ATTRIBUTE_UNUSED, 58 char *comm, 59 int *cycles) 200 char *comm) 60 201 { 61 202 /* Pop with constant. */ 62 203 if (insn == 0x43b2) … … msp430_nooperands (struct msp430_opcode_s *opcode, 64 205 if (insn == opcode->bin_opcode) 65 206 return 2; 66 207 67 if (opcode ->fmt == 0)208 if (opcode_format(opcode) == FMT_EMULATED) 68 209 { 69 210 if ((insn & 0x0f00) != 3 || (insn & 0x0f00) != 2) 70 211 return 0; 71 212 72 213 strcpy (comm, "emulated..."); 73 *cycles = 1;74 214 } 75 215 else 76 216 { 77 217 strcpy (comm, "return from interupt"); 78 *cycles = 5;79 218 } 80 219 81 220 return 2; … … msp430_nooperands (struct msp430_opcode_s *opcode, 83 222 84 223 static int 85 224 msp430_singleoperand (disassemble_info *info, 86 struct msp430_opcode_s *opcode,225 struct msp430_opcode_s const *opcode, 87 226 bfd_vma addr, 88 227 unsigned short insn, 89 228 char *op, 90 char *comm, 91 int *cycles) 229 char *comm) 92 230 { 93 231 int regs = 0, regd = 0; 94 232 int ad = 0, as = 0; 95 int where = 0;96 233 int cmd_len = 2; 97 234 short dst = 0; 98 235 … … msp430_singleoperand (disassemble_info *info, 101 238 as = (insn & 0x0030) >> 4; 102 239 ad = (insn & 0x0080) >> 7; 103 240 104 switch (opcode ->fmt)241 switch (opcode_format(opcode)) 105 242 { 106 case 0:/* Emulated work with dst register. */243 case FMT_EMULATED: /* Emulated work with dst register. */ 107 244 if (regs != 2 && regs != 3 && regs != 1) 108 245 return 0; 109 246 … … msp430_singleoperand (disassemble_info *info, 115 252 if ((opcode->bin_opcode & 0xff00) == 0x5300 && as == 3) 116 253 return 0; 117 254 118 if (ad == 0) 119 { 120 *cycles = 1; 121 122 /* Register. */ 123 if (regd == 0) 124 { 125 *cycles += 1; 126 sprintf (op, "r0"); 127 } 128 else if (regd == 1) 129 sprintf (op, "r1"); 130 131 else if (regd == 2) 132 sprintf (op, "r2"); 133 134 else 135 sprintf (op, "r%d", regd); 136 } 137 else /* ad == 1 msp430dis_opcode. */ 138 { 139 if (regd == 0) 140 { 141 /* PC relative. */ 142 dst = msp430dis_opcode (addr + 2, info); 143 cmd_len += 2; 144 *cycles = 4; 145 sprintf (op, "0x%04x", dst); 146 sprintf (comm, "PC rel. abs addr 0x%04x", 147 PS ((short) (addr + 2) + dst)); 148 } 149 else if (regd == 2) 150 { 151 /* Absolute. */ 152 dst = msp430dis_opcode (addr + 2, info); 153 cmd_len += 2; 154 *cycles = 4; 155 sprintf (op, "&0x%04x", PS (dst)); 156 } 157 else 158 { 159 dst = msp430dis_opcode (addr + 2, info); 160 cmd_len += 2; 161 *cycles = 4; 162 sprintf (op, "%d(r%d)", dst, regd); 163 } 164 } 255 dst = msp430dis_operand (addr + cmd_len, info, regd, ad, &cmd_len); 256 msp430x_decode_operand (regd, ad, addr + cmd_len, dst, OP_16BIT, op, comm); 165 257 break; 166 258 167 case 2: /* rrc, push, call, swpb, rra, sxt, push, call, reti etc... */ 168 if (as == 0) 169 { 170 if (regd == 3) 171 { 172 /* Constsnts. */ 173 sprintf (op, "#0"); 174 sprintf (comm, "r3 As==00"); 175 } 176 else 177 { 178 /* Register. */ 179 sprintf (op, "r%d", regd); 180 } 181 *cycles = 1; 182 } 183 else if (as == 2) 184 { 185 *cycles = 1; 186 if (regd == 2) 187 { 188 sprintf (op, "#4"); 189 sprintf (comm, "r2 As==10"); 190 } 191 else if (regd == 3) 192 { 193 sprintf (op, "#2"); 194 sprintf (comm, "r3 As==10"); 195 } 196 else 197 { 198 *cycles = 3; 199 /* Indexed register mode @Rn. */ 200 sprintf (op, "@r%d", regd); 201 } 202 } 203 else if (as == 3) 204 { 205 *cycles = 1; 206 if (regd == 2) 207 { 208 sprintf (op, "#8"); 209 sprintf (comm, "r2 As==11"); 210 } 211 else if (regd == 3) 212 { 213 sprintf (op, "#-1"); 214 sprintf (comm, "r3 As==11"); 215 } 216 else if (regd == 0) 217 { 218 *cycles = 3; 219 /* absolute. @pc+ */ 220 dst = msp430dis_opcode (addr + 2, info); 221 cmd_len += 2; 222 sprintf (op, "#%d", dst); 223 sprintf (comm, "#0x%04x", PS (dst)); 224 } 225 else 226 { 227 *cycles = 3; 228 sprintf (op, "@r%d+", regd); 229 } 230 } 231 else if (as == 1) 232 { 233 *cycles = 4; 234 if (regd == 0) 235 { 236 /* PC relative. */ 237 dst = msp430dis_opcode (addr + 2, info); 238 cmd_len += 2; 239 sprintf (op, "0x%04x", PS (dst)); 240 sprintf (comm, "PC rel. 0x%04x", 241 PS ((short) addr + 2 + dst)); 242 } 243 else if (regd == 2) 244 { 245 /* Absolute. */ 246 dst = msp430dis_opcode (addr + 2, info); 247 cmd_len += 2; 248 sprintf (op, "&0x%04x", PS (dst)); 249 } 250 else if (regd == 3) 251 { 252 *cycles = 1; 253 sprintf (op, "#1"); 254 sprintf (comm, "r3 As==01"); 255 } 256 else 257 { 258 /* Indexd. */ 259 dst = msp430dis_opcode (addr + 2, info); 260 cmd_len += 2; 261 sprintf (op, "%d(r%d)", dst, regd); 262 } 263 } 259 case FMT_SINGLE_OPERAND: /* rrc, push, call, swpb, rra, sxt, push, call, reti etc... */ 260 dst = msp430dis_operand (addr + cmd_len, info, regd, as, &cmd_len); 261 if(opcode_variant(opcode) != V_CALL) 262 msp430x_decode_operand (regd, as, addr + cmd_len, dst, OP_16BIT, op, comm); 263 else 264 msp430x_decode_operand (regd, as, addr + cmd_len, dst, OP_16BIT_HEX, op, comm); 264 265 break; 265 266 266 case 3: /* Jumps. */ 267 where = insn & 0x03ff; 268 if (where & 0x200) 269 where |= ~0x03ff; 270 if (where > 512 || where < -511) 271 return 0; 272 273 where *= 2; 274 sprintf (op, "$%+-8d", where + 2); 275 sprintf (comm, "abs 0x%x", PS ((short) (addr) + 2 + where)); 276 *cycles = 2; 267 case FMT_JUMP: /* Jumps. */ 268 dst = (short)((insn & 0x03ff) << 6) >> 5; // sign extension, word addr to byte addr conversion 269 sprintf (op, "$%+-8d", dst + 2); 270 sprintf (comm, "abs 0x%x", PS ((short) (addr) + 2 + dst)); 277 271 return 2; 278 break;279 272 default: 280 273 cmd_len = 0; 281 274 } … … msp430_singleoperand (disassemble_info *info, 285 278 286 279 static int 287 280 msp430_doubleoperand (disassemble_info *info, 288 struct msp430_opcode_s *opcode,281 struct msp430_opcode_s const *opcode, 289 282 bfd_vma addr, 290 283 unsigned short insn, 291 284 char *op1, 292 285 char *op2, 293 286 char *comm1, 294 char *comm2, 295 int *cycles) 287 char *comm2) 296 288 { 297 289 int regs = 0, regd = 0; 298 290 int ad = 0, as = 0; 299 291 int cmd_len = 2; 300 short dst = 0; 292 short ops; 293 short opd; 301 294 302 295 regd = insn & 0x0f; 303 296 regs = (insn & 0x0f00) >> 8; 304 297 as = (insn & 0x0030) >> 4; 305 298 ad = (insn & 0x0080) >> 7; 306 299 307 if (opcode ->fmt == 0)300 if (opcode_format(opcode) == FMT_EMULATED) 308 301 { 309 302 /* Special case: rla and rlc are the only 2 emulated instructions that 310 303 fall into two operand instructions. */ … … msp430_doubleoperand (disassemble_info *info, 319 312 if (regd != regs || as != ad) 320 313 return 0; /* May be 'data' section. */ 321 314 322 if (ad == 0 )315 if (ad == 0 && regd == 3) // #N 323 316 { 324 /* Register mode. */ 325 if (regd == 3) 326 { 327 strcpy (comm1, _("Illegal as emulation instr")); 328 return -1; 329 } 330 331 sprintf (op1, "r%d", regd); 332 *cycles = 1; 333 } 334 else /* ad == 1 */ 335 { 336 if (regd == 0) 337 { 338 /* PC relative, Symbolic. */ 339 dst = msp430dis_opcode (addr + 2, info); 340 cmd_len += 4; 341 *cycles = 6; 342 sprintf (op1, "0x%04x", PS (dst)); 343 sprintf (comm1, "PC rel. 0x%04x", 344 PS ((short) addr + 2 + dst)); 345 346 } 347 else if (regd == 2) 348 { 349 /* Absolute. */ 350 dst = msp430dis_opcode (addr + 2, info); 351 /* If the 'src' field is not the same as the dst 352 then this is not an rla instruction. */ 353 if (dst != msp430dis_opcode (addr + 4, info)) 354 return 0; 355 cmd_len += 4; 356 *cycles = 6; 357 sprintf (op1, "&0x%04x", PS (dst)); 358 } 359 else 360 { 361 /* Indexed. */ 362 dst = msp430dis_opcode (addr + 2, info); 363 cmd_len += 4; 364 *cycles = 6; 365 sprintf (op1, "%d(r%d)", dst, regd); 366 } 317 strcpy (comm1, _("Illegal as emulation instr")); 318 return -1; 367 319 } 320 ops = msp430dis_operand (addr + cmd_len, info, regs, as, &cmd_len); 321 opd = msp430dis_operand (addr + cmd_len, info, regd, ad, &cmd_len); 322 /* If the 'src' field is not the same as the dst 323 then this is not an rla instruction. */ 324 if (ops != opd) 325 return 0; 326 msp430x_decode_operand (regs, as, addr + cmd_len, ops, OP_16BIT, op1, comm1); 368 327 369 328 *op2 = 0; 370 329 *comm2 = 0; 371 330 return cmd_len; 372 331 } 373 374 332 /* Two operands exactly. */ 333 375 334 if (ad == 0 && regd == 3) 376 335 { 377 336 /* R2/R3 are illegal as dest: may be data section. */ 378 337 strcpy (comm1, _("Illegal as 2-op instr")); 379 338 return -1; 380 339 } 340 ops = msp430dis_operand (addr + cmd_len, info, regs, as, &cmd_len); 341 msp430x_decode_operand (regs, as, addr + cmd_len, ops, OP_16BIT, op1, comm1); 381 342 382 /* Source. */ 383 if (as == 0) 384 { 385 *cycles = 1; 386 if (regs == 3) 387 { 388 /* Constsnts. */ 389 sprintf (op1, "#0"); 390 sprintf (comm1, "r3 As==00"); 391 } 392 else 393 { 394 /* Register. */ 395 sprintf (op1, "r%d", regs); 396 } 397 } 398 else if (as == 2) 399 { 400 *cycles = 1; 343 opd = msp430dis_operand (addr + cmd_len, info, regd, ad, &cmd_len); 344 msp430x_decode_operand (regd, ad, addr + cmd_len, opd, OP_16BIT, op2, comm2); 345 return cmd_len; 346 } 401 347 402 if (regs == 2) 403 { 404 sprintf (op1, "#4"); 405 sprintf (comm1, "r2 As==10"); 406 } 407 else if (regs == 3) 408 { 409 sprintf (op1, "#2"); 410 sprintf (comm1, "r3 As==10"); 411 } 412 else 413 { 414 *cycles = 2; 348 static int 349 msp430_branchinstr (disassemble_info *info, 350 struct msp430_opcode_s const *opcode ATTRIBUTE_UNUSED, 351 bfd_vma addr ATTRIBUTE_UNUSED, 352 unsigned short insn, 353 char *op1, 354 char *comm1) 355 { 356 int regs = (insn & 0x0f00) >> 8; 357 int as = (insn & 0x0030) >> 4; 358 int cmd_len = 2; 359 short dst; 415 360 416 /* Indexed register mode @Rn. */ 417 sprintf (op1, "@r%d", regs); 418 } 419 if (!regs) 420 *cycles = 3; 421 } 422 else if (as == 3) 361 dst = msp430dis_operand (addr + cmd_len, info, regs, as, &cmd_len); 362 msp430x_decode_operand(regs, as, addr + cmd_len, dst, OP_16BIT_HEX, op1, comm1); 363 364 return cmd_len; 365 } 366 367 static opwidth_t 368 msp430x_opwidth(unsigned int insn) 369 { 370 insn &= NON_ADDR_OPERATION | BYTE_OPERATION_X; 371 372 if(insn == (NON_ADDR_OPERATION | BYTE_OPERATION_X)) 373 return BYTE_OP; 374 if(insn == NON_ADDR_OPERATION) 375 return WORD_OP; 376 if(insn == BYTE_OPERATION_X) 377 return ADDR_OP; 378 379 return 0; // reserved 380 } 381 382 static int 383 msp430x_singleoperand (disassemble_info *info, 384 struct msp430_opcode_s const *opcode, 385 bfd_vma addr, 386 unsigned int insn, 387 char *op, 388 char *comm, 389 int *repeats) 390 { 391 int reg = (insn >> 16) & 0xf; 392 int am = (insn >> 20) & 0x3; 393 int cmd_len = 4; 394 int dst = 0; 395 396 if ( opcode_variant(opcode) < V_PUSHX ) 397 if ((am == 3 && reg == 0) // #N operand 398 || (am == 0 && reg == 3) // R3 is illegal as dest: may be data section. 399 ) 400 { 401 strcpy (comm, _("Illegal as 1-op instr")); 402 return -1; 403 } 404 405 // extract repeat count if any 406 if ( am == 0 ) // extension word for register mode 423 407 { 424 if (regs == 2) 425 { 426 sprintf (op1, "#8"); 427 sprintf (comm1, "r2 As==11"); 428 *cycles = 1; 429 } 430 else if (regs == 3) 431 { 432 sprintf (op1, "#-1"); 433 sprintf (comm1, "r3 As==11"); 434 *cycles = 1; 435 } 436 else if (regs == 0) 437 { 438 *cycles = 3; 439 /* Absolute. @pc+. */ 440 dst = msp430dis_opcode (addr + 2, info); 441 cmd_len += 2; 442 sprintf (op1, "#%d", dst); 443 sprintf (comm1, "#0x%04x", PS (dst)); 444 } 445 else 446 { 447 *cycles = 2; 448 sprintf (op1, "@r%d+", regs); 449 } 450 } 451 else if (as == 1) 452 { 453 if (regs == 0) 454 { 455 *cycles = 4; 456 /* PC relative. */ 457 dst = msp430dis_opcode (addr + 2, info); 458 cmd_len += 2; 459 sprintf (op1, "0x%04x", PS (dst)); 460 sprintf (comm1, "PC rel. 0x%04x", 461 PS ((short) addr + 2 + dst)); 462 } 463 else if (regs == 2) 464 { 465 *cycles = 2; 466 /* Absolute. */ 467 dst = msp430dis_opcode (addr + 2, info); 468 cmd_len += 2; 469 sprintf (op1, "&0x%04x", PS (dst)); 470 sprintf (comm1, "0x%04x", PS (dst)); 471 } 472 else if (regs == 3) 473 { 474 *cycles = 1; 475 sprintf (op1, "#1"); 476 sprintf (comm1, "r3 As==01"); 477 } 478 else 479 { 480 *cycles = 3; 481 /* Indexed. */ 482 dst = msp430dis_opcode (addr + 2, info); 483 cmd_len += 2; 484 sprintf (op1, "%d(r%d)", dst, regs); 485 } 408 if (insn & 0x008f) // repetitions 409 { 410 if (insn & 0x0080) 411 *repeats = insn & 0xf; // positive number is Rn 412 else 413 *repeats = 0 - (insn & 0xf); // negative number is #N 414 } 486 415 } 487 416 488 /* Destination. Special care needed on addr + XXXX. */ 417 // extract operands 418 dst = msp430dis_operand(addr + cmd_len, info, reg, am, &cmd_len) | ((insn & 0x0000000f) << 16); 419 dst = (dst << 12) >> 12; // sign extension 420 msp430x_decode_operand(reg, am, addr + cmd_len, dst, OP_20BIT, op, comm); 421 422 return cmd_len; 423 } 424 425 static int 426 msp430x_exception (disassemble_info *info, 427 struct msp430_opcode_s const *opcode, 428 bfd_vma addr, 429 unsigned int insn, 430 char *op1, 431 char *op2, 432 char *comm1, 433 char *comm2, 434 opwidth_t *op_width) 435 { 436 int reg = 0; 437 int cmd_len = 2; 438 int n = 0; 439 int dst = 0; 440 441 reg = insn & 0xf; 489 442 490 if (ad == 0)443 switch(opcode_variant(opcode)) 491 444 { 492 /* Register. */ 493 if (regd == 0) 494 { 495 *cycles += 1; 496 sprintf (op2, "r0"); 497 } 498 else if (regd == 1) 499 sprintf (op2, "r1"); 445 case V_CALLA: 446 switch((insn >> 4) & 0xf) 447 { 448 case 4: // Rdst 449 msp430x_decode_operand(reg, 0, 0, 0, 0, op1, comm1); 450 break; 451 case 5: // x(Rdst) 452 dst = (short)msp430dis_operand(addr + cmd_len, info, reg, 1, &cmd_len); 453 msp430x_decode_operand(reg, 1, addr + cmd_len, dst, OP_16BIT, op1, comm1); 454 break; 455 case 6: // @Rdst 456 msp430x_decode_operand(reg, 2, 0, 0, 0, op1, comm1); 457 break; 458 case 7: // @Rdst+ 459 msp430x_decode_operand(reg, 3, 0, 0, 0, op1, comm1); 460 break; 461 case 8: // &abs20 462 dst = msp430dis_operand(addr + cmd_len, info, 2, 1, &cmd_len) | ((insn & 0x000f) << 16); 463 msp430x_decode_operand(2, 1, addr + cmd_len, dst, OP_20BIT_HEX, op1, comm1); 464 break; 465 case 9: // EDE 466 dst = msp430dis_operand(addr + cmd_len, info, 0, 1, &cmd_len) | ((insn & 0x000f) << 16); 467 msp430x_decode_operand(0, 1, addr + cmd_len, dst, OP_20BIT, op1, comm1); 468 break; 469 case 0xb: // #imm20 470 dst = msp430dis_operand(addr + cmd_len, info, 0, 3, &cmd_len) | ((insn & 0x000f) << 16); 471 msp430x_decode_operand(0, 3, addr + cmd_len, dst, OP_20BIT_HEX, op1, comm1); 472 break; 473 } 474 break; 475 case V_PUSHM: 476 n = ((insn >> 4) & 0xf) + 1; 477 msp430x_decode_operand(0, 3, 0, n, OP_DECIMAL, op1, comm1); // #N 478 msp430x_decode_operand(reg, 0, 0, 0, 0, op2, comm2); // Rdst 479 if ((insn & 0x0100) == 0) 480 *op_width = ADDR_OP; 481 break; 482 case V_POPM: 483 n = ((insn >> 4) & 0xf) + 1; 484 reg = (reg + n - 1) & 0xf; 485 msp430x_decode_operand(0, 3, 0, n, OP_DECIMAL, op1, comm1); // #N 486 msp430x_decode_operand(reg, 0, 0, 0, 0, op2, comm2); // Rdst 487 if ((insn & 0x0100) == 0) 488 *op_width = ADDR_OP; 489 break; 490 case V_ROTM: 491 n = ((insn >> 10) & 0x3) + 1; 492 msp430x_decode_operand(0, 3, 0, n, OP_DECIMAL, op1, comm1); // #N 493 msp430x_decode_operand(reg, 0, 0, 0, 0, op2, comm2); // Rdst 494 if ((insn & 0x0010) == 0) 495 *op_width = ADDR_OP; 496 break; 497 default: 498 break; 499 } 500 return cmd_len; 501 } 500 502 501 else if (regd == 2) 502 sprintf (op2, "r2"); 503 static int 504 msp430x_doubleoperand (disassemble_info *info, 505 struct msp430_opcode_s const *opcode, 506 bfd_vma addr, 507 unsigned int insn, 508 char *op1, 509 char *op2, 510 char *comm1, 511 char *comm2, 512 opwidth_t *op_width, 513 int *repeats) 514 { 515 int regs, regd; 516 int as, ad; 517 int ops, opd; 518 int cmd_len = 4; 503 519 504 else 505 sprintf (op2, "r%d", regd); 520 regd = (insn >> 16) & 0xf; 521 regs = (insn >> 24) & 0xf; 522 as = (insn >> 20) & 0x3; 523 ad = (insn >> 23) & 0x1; 524 525 if (ad == 0 && regd == 3) 526 { 527 // R3 is illegal as dest: may be data section. 528 if (comm1) 529 strcpy (comm1, _("Illegal as 2-op instr")); 530 else if (comm2) 531 strcpy (comm2, _("Illegal as 2-op instr")); 532 return -1; 506 533 } 507 else /* ad == 1. */ 534 *op_width = msp430x_opwidth(insn); 535 536 // extract repeat count if any 537 if ( as == 0 && ad == 0 ) // extension word for register mode 508 538 { 509 * cycles += 3; 510 511 if (regd == 0) 512 { 513 /* PC relative. */ 514 *cycles += 1; 515 dst = msp430dis_opcode (addr + cmd_len, info); 516 sprintf (op2, "0x%04x", PS (dst)); 517 sprintf (comm2, "PC rel. 0x%04x", 518 PS ((short) addr + cmd_len + dst)); 519 cmd_len += 2; 520 } 521 else if (regd == 2) 522 { 523 /* Absolute. */ 524 dst = msp430dis_opcode (addr + cmd_len, info); 525 cmd_len += 2; 526 sprintf (op2, "&0x%04x", PS (dst)); 527 } 528 else 529 { 530 dst = msp430dis_opcode (addr + cmd_len, info); 531 cmd_len += 2; 532 sprintf (op2, "%d(r%d)", dst, regd); 533 } 539 if (insn & 0x008f) // repetitions 540 { 541 if (insn & 0x0080) 542 *repeats = insn & 0xf; // positive number is Rn 543 else 544 *repeats = 0 - (insn & 0xf); // negative number is #N 545 } 534 546 } 547 // extract operands 548 ops = msp430dis_operand(addr + cmd_len, info, regs, as, &cmd_len) | ((insn & 0x00000780) << 9); 549 ops = (ops << 12) >> 12; // sign extension 550 msp430x_decode_operand(regs, as, addr + cmd_len, ops, OP_20BIT, op1, comm1); 551 552 opd = msp430dis_operand(addr + cmd_len, info, regd, ad, &cmd_len) | ((insn & 0x0000000f) << 16); 553 opd = (opd << 12) >> 12; // sign extension 554 if (opcode_variant(opcode) == V_X_SHIFT 555 && ((0 == (as | ad) && ops != opd) /* non-register extension different ops */ 556 || regs != regd)) /* register extension different regs */ 557 return 0; // different operand => not emulated shift 558 559 msp430x_decode_operand(regd, ad, addr + cmd_len, opd, OP_20BIT, op2, comm2); 535 560 536 561 return cmd_len; 537 562 } 538 563 539 564 static int 540 msp430_branchinstr (disassemble_info *info, 541 struct msp430_opcode_s *opcode ATTRIBUTE_UNUSED, 542 bfd_vma addr ATTRIBUTE_UNUSED, 565 msp430x_address (disassemble_info *info, 566 bfd_vma addr, 543 567 unsigned short insn, 544 568 char *op1, 569 char *op2, 545 570 char *comm1, 546 int *cycles)571 char *comm2) 547 572 { 548 int regs = 0, regd = 0;549 int ad = 0, as = 0;550 573 int cmd_len = 2; 551 short dst = 0; 552 553 regd = insn & 0x0f; 554 regs = (insn & 0x0f00) >> 8; 555 as = (insn & 0x0030) >> 4; 556 ad = (insn & 0x0080) >> 7; 557 558 if (regd != 0) /* Destination register is not a PC. */ 559 return 0; 560 561 /* dst is a source register. */ 562 if (as == 0) 574 int dst = 0; 575 typedef struct 563 576 { 564 /* Constants. */ 565 if (regs == 3) 566 { 567 *cycles = 1; 568 sprintf (op1, "#0"); 569 sprintf (comm1, "r3 As==00"); 570 } 571 else 572 { 573 /* Register. */ 574 *cycles = 1; 575 sprintf (op1, "r%d", regs); 576 } 577 int as, regs; 578 int ad, regd; 579 int length; 577 580 } 578 else if (as == 2) 581 operands_t; 582 583 static operands_t const operands_table[] = 579 584 { 580 if (regs == 2) 581 { 582 *cycles = 2; 583 sprintf (op1, "#4"); 584 sprintf (comm1, "r2 As==10"); 585 } 586 else if (regs == 3) 587 { 588 *cycles = 1; 589 sprintf (op1, "#2"); 590 sprintf (comm1, "r3 As==10"); 591 } 592 else 593 { 594 /* Indexed register mode @Rn. */ 595 *cycles = 2; 596 sprintf (op1, "@r%d", regs); 597 } 598 } 599 else if (as == 3) 585 { 2, -1, 0, -1, 0 }, // 0 @Rsrc, Rdst 586 { 3, -1, 0, -1, 0 }, // 1 @Rsrc+, Rdst 587 { 1, 2, 0, -1, 2 }, // 2 &abs20, Rdst 588 { 1, -1, 0, -1, 2 }, // 3 x(Rsrc), Rdst 589 { 0, 0, 0, 0, 0 }, // 4 590 { 0, 0, 0, 0, 0 }, // 5 591 { 0, -1, 1, 2, 2 }, // 6 Rsrc, &abs20 592 { 0, -1, 1, -1, 2 }, // 7 Rsrc, x(Rdst) 593 { 3, 0, 0, -1, 2 }, // 8 #imm20, Rdst 594 { 3, 0, 0, -1, 2 }, // 9 #imm20, Rdst 595 { 3, 0, 0, -1, 2 }, // a #imm20, Rdst 596 { 3, 0, 0, -1, 2 }, // b #imm20, Rdst 597 { 0, -1, 0, -1, 0 }, // c Rsrc, Rdst 598 { 0, -1, 0, -1, 0 }, // d Rsrc, Rdst 599 { 0, -1, 0, -1, 0 }, // e Rsrc, Rdst 600 { 0, -1, 0, -1, 0 }, // f Rsrc, Rdst 601 }; 602 603 operands_t operands = operands_table[(insn >> 4) & 0xf]; 604 if(((insn >> 4) & 0xf) == 6) 605 dst = msp430dis_opcode (addr + cmd_len, info) | ((insn & 0x000f) << 16); 606 else if(((insn >> 4) & 0xb) == 3) 607 dst = (short)msp430dis_opcode (addr + cmd_len, info); 608 else if(operands.length != 0) 609 dst = msp430dis_opcode(addr + cmd_len, info) | ((insn & 0x0f00) << 8); 610 611 if(operands.regs == -1) 612 operands.regs = (insn >> 8 ) & 0x000f; 613 if(operands.regd == -1) 614 operands.regd = (insn >> 0 ) & 0x000f; 615 616 if (operands.regd == 3) 600 617 { 601 if (regs == 2) 602 { 603 *cycles = 1; 604 sprintf (op1, "#8"); 605 sprintf (comm1, "r2 As==11"); 606 } 607 else if (regs == 3) 608 { 609 *cycles = 1; 610 sprintf (op1, "#-1"); 611 sprintf (comm1, "r3 As==11"); 612 } 613 else if (regs == 0) 614 { 615 /* Absolute. @pc+ */ 616 *cycles = 3; 617 dst = msp430dis_opcode (addr + 2, info); 618 cmd_len += 2; 619 sprintf (op1, "#0x%04x", PS (dst)); 620 } 621 else 622 { 623 *cycles = 2; 624 sprintf (op1, "@r%d+", regs); 625 } 618 // R3 is illegal as dest: may be data section. 619 if (comm1) 620 strcpy (comm1, _("Illegal as address instr")); 621 else if (comm2) 622 strcpy (comm2, _("Illegal as address instr")); 623 return -1; 626 624 } 627 else if (as == 1) 628 { 629 * cycles = 3; 625 // extract operands 626 msp430x_decode_operand(operands.regs, operands.as, addr + cmd_len, dst, 627 ((insn >> 4) & 0xf) == 3 ? OP_16BIT_HEX : OP_20BIT_HEX, op1, comm1); 628 msp430x_decode_operand(operands.regd, operands.ad, addr + cmd_len, dst, 629 ((insn >> 4) & 0xf) == 7 ? OP_16BIT_HEX : OP_20BIT_HEX, op2, comm2); 630 return cmd_len + operands.length; 631 } 630 632 631 if (regs == 0) 632 { 633 /* PC relative. */ 634 dst = msp430dis_opcode (addr + 2, info); 635 cmd_len += 2; 636 (*cycles)++; 637 sprintf (op1, "0x%04x", PS (dst)); 638 sprintf (comm1, "PC rel. 0x%04x", 639 PS ((short) addr + 2 + dst)); 640 } 641 else if (regs == 2) 642 { 643 /* Absolute. */ 644 dst = msp430dis_opcode (addr + 2, info); 645 cmd_len += 2; 646 sprintf (op1, "&0x%04x", PS (dst)); 647 } 648 else if (regs == 3) 649 { 650 (*cycles)--; 651 sprintf (op1, "#1"); 652 sprintf (comm1, "r3 As==01"); 653 } 654 else 655 { 656 /* Indexd. */ 657 dst = msp430dis_opcode (addr + 2, info); 658 cmd_len += 2; 659 sprintf (op1, "%d(r%d)", dst, regs); 660 } 661 } 633 static int 634 msp430x_emulated (disassemble_info *info, 635 struct msp430_opcode_s const *opcode, 636 bfd_vma addr, 637 unsigned int insn, 638 char *op1, 639 char *comm1, 640 opwidth_t *op_width, 641 int *repeats) 642 { 662 643 663 return cmd_len; 644 switch(opcode_variant(opcode)) 645 { 646 case V_NONE: 647 case V_X_SHIFT: 648 // emulated by double operand instruction 649 return msp430x_doubleoperand(info, opcode, addr, insn, (char *)0, op1, 650 (char *)0, comm1, op_width, repeats); 651 case V_RETA: // reta, substituted by mova 652 return 2; 653 case V_EMU_ADDR: // substituted by other address instruction 654 return msp430x_address(info, addr, insn, (char *)0, op1, 655 (char *)0, comm1); 656 case V_BRA: // bra, substituted by mova 657 return msp430x_address(info, addr, insn, op1, (char *)0, 658 comm1, (char *)0); 659 default: 660 break; 661 } 662 return 0; 664 663 } 665 664 666 665 int … … print_insn_msp430 (bfd_vma addr, disassemble_info *info) 668 667 { 669 668 void *stream = info->stream; 670 669 fprintf_ftype prin = info->fprintf_func; 671 struct msp430_opcode_s *opcode;670 struct msp430_opcode_s const *opcode; 672 671 char op1[32], op2[32], comm1[64], comm2[64]; 673 672 int cmd_len = 0; 674 unsigned short insn; 675 int cycles = 0; 676 char *bc = ""; 677 char dinfo[32]; /* Debug purposes. */ 678 673 unsigned int insn; 674 int repeats = 0; 675 core_t core = CORE_430; 676 677 opwidth_t op_width = DEFAULT_OP; // word instruction by default 678 static char const *width_modifier[] = 679 {"", "", ".b", ".a" }; 680 679 681 insn = msp430dis_opcode (addr, info); 680 sprintf (dinfo, "0x%04x", insn);681 682 682 if (((int) addr & 0xffff) > 0xffdf) 683 if (info->mach == 241 || info->mach == 26 || info->mach == 46 || info->mach == 471) 684 { 685 core = CORE_430X; 686 } 687 else if (info->mach == 54) 688 { 689 core = CORE_430X2; 690 } 691 692 if ( (core == CORE_430 && ((int) addr & 0xffff) >= 0xffe0) 693 || ( core == CORE_430X && (((int) addr & 0xfffff) >= 0xffc0) && ((int) addr & 0xfffff) < 0x10000) 694 || ( core == CORE_430X2 && (((int) addr & 0xfffff) >= 0xff80) && ((int) addr & 0xfffff) < 0x10000) 695 ) 683 696 { 684 697 (*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn); 685 698 return 2; 686 699 } 687 700 701 if (core > CORE_430 && ((insn & 0xf800) == 0x1800)) // Extended instruction 702 insn |= msp430dis_opcode(addr + 2, info) << 16; 703 688 704 *comm1 = 0; 689 705 *comm2 = 0; 690 706 691 707 for (opcode = msp430_opcodes; opcode->name; opcode++) 692 708 { 693 709 if ((insn & opcode->bin_mask) == opcode->bin_opcode 694 && opcode->bin_opcode != 0x9300) 710 // && opcode->bin_opcode != 0x9300 // was disasm tst instruction as cmp #0, dst? 711 ) 695 712 { 696 713 *op1 = 0; 697 714 *op2 = 0; 698 715 *comm1 = 0; 699 716 *comm2 = 0; 700 717 701 /* r0 as destination. Ad should be zero. */ 702 if (opcode->insn_opnumb == 3 && (insn & 0x000f) == 0 703 && (0x0080 & insn) == 0) 718 /* unsupported instruction */ 719 if(opcode_format(opcode) >= FMT_X && core < CORE_430X) 720 break; 721 722 /* r0 as destination. Ad should be zero. Rdst=0 and Ad=0 are encoded in opcode & opcode_mask */ 723 if (opcode_format(opcode) == FMT_EMULATED && opcode_variant(opcode) == V_BR) 704 724 { 705 725 cmd_len = 706 msp430_branchinstr (info, opcode, addr, insn, op1, comm1, 707 &cycles); 726 msp430_branchinstr (info, opcode, addr, insn, op1, comm1); 708 727 if (cmd_len) 709 728 break; 710 729 } 711 712 switch (opcode->insn_opnumb) 713 { 714 case 0: 715 cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles); 716 break; 717 case 2: 718 cmd_len = 719 msp430_doubleoperand (info, opcode, addr, insn, op1, op2, 720 comm1, comm2, &cycles); 721 if (insn & BYTE_OPERATION) 722 bc = ".b"; 723 break; 724 case 1: 725 cmd_len = 726 msp430_singleoperand (info, opcode, addr, insn, op1, comm1, 727 &cycles); 728 if (insn & BYTE_OPERATION && opcode->fmt != 3) 729 bc = ".b"; 730 break; 731 default: 732 break; 733 } 730 if(opcode_format(opcode) < FMT_X) 731 switch (opcode->insn_opnumb) 732 { 733 case 0: 734 cmd_len = msp430_nooperands (opcode, addr, insn, comm1); 735 break; 736 case 2: 737 cmd_len = 738 msp430_doubleoperand (info, opcode, addr, insn, op1, op2, 739 comm1, comm2); 740 if (insn & BYTE_OPERATION) 741 op_width = BYTE_OP; 742 break; 743 case 1: 744 cmd_len = 745 msp430_singleoperand (info, opcode, addr, insn, op1, comm1); 746 if (insn & BYTE_OPERATION && opcode_format(opcode) != FMT_JUMP) 747 op_width = BYTE_OP; 748 break; 749 default: 750 break; 751 } 752 else // 430x instruction 753 switch(opcode_format(opcode)) 754 { 755 case FMT_X_SINGLE_OPERAND: 756 if( opcode_variant(opcode) == V_SWPSXT // swpbx, sxtx 757 && (insn & (NON_ADDR_OPERATION | BYTE_OPERATION_X)) == 0) // .a, special case 758 insn ^= BYTE_OPERATION_X; // make A/L, B/W as ordinary 759 760 op_width = msp430x_opwidth(insn); 761 762 if( opcode_variant(opcode) == V_SWPSXT && op_width == BYTE_OP) // swpbx, sxtx 763 strcpy (comm1, _("Illegal A/L, B/W bits setting")); 764 765 cmd_len = msp430x_singleoperand (info, opcode, addr, insn, op1, comm1, 766 &repeats); 767 break; 768 case FMT_X_EXCEPTION: 769 cmd_len = msp430x_exception (info, opcode, addr, insn, op1, op2, 770 comm1, comm2, &op_width); 771 break; 772 case FMT_X_DOUBLE_OPERAND: 773 cmd_len = msp430x_doubleoperand (info, opcode, addr, insn, op1, op2, 774 comm1, comm2, &op_width, &repeats); 775 break; 776 case FMT_X_EMULATED: 777 cmd_len = msp430x_emulated (info, opcode, addr, insn, op1, 778 comm1, &op_width, &repeats); 779 break; 780 781 case FMT_X_ADDRESS: 782 cmd_len = msp430x_address (info, addr, insn, op1, op2, 783 comm1, comm2); 784 break; 785 default: 786 break; 787 } 734 788 } 735 789 736 790 if (cmd_len) 737 791 break; 738 792 } 739 793 740 dinfo[5] = 0;741 742 794 if (cmd_len < 1) 743 795 { 744 796 /* Unknown opcode, or invalid combination of operands. */ 745 (*prin) (stream, ".word 0x%04x; ???? ", PS (insn));797 (*prin) (stream, ".word 0x%04x; ????\t%s%s", PS (insn), comm1, comm2); 746 798 return 2; 747 799 } 748 800 749 (*prin) (stream, "%s%s", opcode->name, bc); 801 802 if (repeats) 803 { 804 if (repeats < 0) 805 (*prin) (stream, ".rpt\t#%d\n\t\t\t\t", 0 - repeats); 806 else 807 (*prin) (stream, ".rpt\tr%d\n\t\t\t\t", repeats); 808 } 809 810 (*prin) (stream, "%s%s", opcode->name, width_modifier[op_width]); 750 811 751 812 if (*op1) 752 813 (*prin) (stream, "\t%s", op1); … … print_insn_msp430 (bfd_vma addr, disassemble_info *info) 765 826 766 827 if (*comm1 || *comm2) 767 828 (*prin) (stream, ";"); 768 else if (cycles)769 {770 if (*op2)771 (*prin) (stream, ";");772 else773 {774 if (strlen (op1) < 7)775 (*prin) (stream, ";");776 else777 (*prin) (stream, "\t;");778 }779 }780 829 if (*comm1) 781 830 (*prin) (stream, "%s", comm1); 782 831 if (*comm1 && *comm2) 783 (*prin) (stream, ", ");832 (*prin) (stream, ", "); 784 833 if (*comm2) 785 (*prin) (stream, " 834 (*prin) (stream, "%s", comm2); 786 835 return cmd_len; 787 836 }